HDL 代码生成
您可以使用 HDL Coder™ 功能在 FPGA 或 ASIC 上实现通信系统设计。您可以生成可综合和可移植的 VHDL® 和 Verilog® 代码，以及生成 VHDL 和 Verilog 测试平台，用于对生成的代码进行快速仿真、测试和验证。您可以从 Simulink 或 MATLAB 设计生成代码。此支持包括纠错和错误检测、调制、滤波器、数学和信号运算，以及针对资源使用和性能优化的其他算法，例如 NCO (DSP HDL Toolbox) 模块。有关如何生成 HDL 代码的基本示例，请参阅Programmable FIR Filter for FPGA。
要在 Simulink 或 MATLAB 中调试您的设计，请使用逻辑分析仪波形查看器。
主题
- Find Blocks That Support HDL Code Generation
Filter for blocks that support HDL code generation in the Simulink library browser and in documentation.
- Wireless Communications Design for ASICs, FPGAs, and SoCs
Design wireless communication algorithms for hardware by using Wireless HDL Toolbox™ blocks.
Simulink 可视化工具
| 逻辑分析仪 | 可视化、测量并分析一段时间内的转移和状态 |
相关信息
精选示例
HDL Neural Network Design for Digital Predistorter
Use neural-network-based (NN-based) digital predistorter (DPD) to compensate effects of nonlinearities in power amplifier.
Deploy and Verify HDL Neural Network Based DPD on FPGA
Deploy neural-network-based digital predistorter (NN DPD) algorithm and verify using OFDM signal.
Modulation Classification by Using FPGA
Deploy a pretrained convolutional neural network (CNN) for modulation classification to the Xilinx® Zynq® UltraScale+™ MPSoC ZCU102 Evaluation Kit.
HDL QPSK Transmitter and Receiver
Implement a QPSK transmitter and receiver for HDL code generation and hardware implementation.
HDL QAM Transmitter and Receiver
Implement a 64-QAM transmitter and receiver for HDL code generation and hardware implementation.
Generate HDL Code for Viterbi Decoder
Implement the Viterbi decoding algorithm for HDL code generation and hardware implementation.
Airplane Tracking with ADS-B Captured Data
Implement an Automatic Dependent Surveillance-Broadcast (ADS-B) receiver for HDL code generation and hardware implementation.
