DSP HDL IP Designer

Open the App

In the apps gallery, under the Signal Processing and Communications group, click the DSP HDL IP Designer app. Alternatively, at the MATLAB® command prompt, enter dsphdlIPDesigner.

Select Algorithm

Select the Discrete FIR Filter from the IP Blocks gallery in the app.

All the algorithms have streaming interfaces with a data port and a control signal that indicates when the input data is valid. The data ports accept and return a scalar or small vector of input data samples on each clock cycle. In the app, you can see the interface signals connecting the IP block to the Input Stimulus block.

To configure your algorithms, set options in the Properties sidebar. Setting the Filter Structure parameter to Direct-form systolic implements a fully parallel filter with high throughput. Configure the filter coefficients as a 25-tap lowpass FIR filter by setting the Coefficients parameter to firpm(24,[0 .1 .3 .5]*2,[1 1 0 0]). The coefficients are specified as double data type and, by default, the filter casts them to match the input data type. You can also specify a coefficient data type on the Data Types tab.

Configure Input Stimulus

Click the Input Stimulus block. The Input settings section in the Properties sidebar provides dimensions and data types for the input to the algorithm. The app provides default values for each input port. The dimensions and data types of these values define your HDL interface, and the generated testbench applies these values to your algorithm. You do not need to specify values for control signals like valid and reset. The generated testbench automatically drives the control signals. For this algorithm, you must specify the data input.

The data input for this FIR filter can be a 1-D or 3-D matrix. A 1-D matrix represents a stream of data samples over time. A 3-D matrix represents number of input samples per cycle-by-number of data channels-by-data samples over time. The Discrete FIR Filter algorithm supports frame-based data, or multichannel data, but not both at the same time.

This example specifies a 1-D matrix that represents 200 fixed-point data type input samples. This data format configures the filter to accept one input sample each clock cycle and the filter has a single data channel.

numSamples = 200;
testbench.data = fi(randn(numSamples,1),1,16,15);

Alternatively, to configure the filter to accept a frame of four input samples each clock cycle, you can set the input data to a 4-by-1-by-data samples over time matrix. A filter with frame-based input must have a single data channel. A filter with 4-sample vector input implements a polyphase decomposition into four parallel subfilters and does not implement symmetry optimizations. This implementation uses more resources to support increased throughput.

numSamples = 200;
dataIn = fi(randn(numSamples,1),1,16,15);
testbench.data = reshape(dataIn,4,1,[]);

To specify a multichannel filter, first set the Coefficients parameter to a number of channels-by-coefficients matrix, like [firpm(24,[0 .1 .3 .5]*2,[1 1 0 0]); firpm(24,[0 .1 .2 .4]*2,[1 1 0 0])]. Then, configure the input stimulus as a 3-D matrix of 1-by-number of channels-by-data samples over time values. A filter with multiple channels cannot use frame-based input. Each channel accepts a single sample each cycle. This filter uses the same resources as the scalar input filter.

numSamples = 200;
dataIn = fi(randn(numSamples,1),1,16,15);
testbench.data = reshape(dataIn,1,2,[]);

Generate HDL Code

You can configure HDL code generation options in Configure HDL. By default, the app generates an HDL simulator testbench and scripts for compiling and running the design in the Siemens® ModelSim® and AMD® Vivado® simulators. The HDL simulator testbench applies the input signals you defined in Input Stimulus, drives the input control signals, and compares all the output ports of the generated HDL IP block against the output from running your algorithm in a MATLAB® simulation.

To generate HDL code and a testbench, click Generate HDL. The code generation log appears in the Console window, including any warning or error messages.

The generated files and reports are under codegen\hdl_IP\hdlsrc in your working folder. You can find more information about any errors or warnings in the hdl_IP_hdl_conformance_report.html file.

The generated VHDL entity shows the IP block interface, including control signals and the input data type that you specified. The output data type is determined by the Output parameter on the Data Type tab of the algorithm. By default, it is derived from the input data type with no loss of precision.

The Resources tab shows an estimate of hardware resources used by this filter implementation. A filter with scalar input shares multipliers between symmetric coefficients, so this 25-tap filter uses 13 multipliers.

Serial Filter Implementation

To implement a filter that uses fewer resources but has lower throughput, you can select a serial implementation. On the FIR Filter block in the app, set the Structure parameter to Partly serial systolic. Then, you can specify the serialization by either the number of multipliers or number of cycles between valid input samples. For a filter with L coefficients, the IP block implements a serial filter with M or fewer multipliers and requires input samples that are at least N cycles apart, such that L = N × M. To implement a fully serial filter, select Minimum number of cycles between valid input samples and set Number of cycles to 13 (the number of multipliers used by the scalar input filter previously described).

When you apply these changes, the block in the app now has an output ready port that indicates when the filter is ready for new input data. The generated HDL testbench automatically responds to the ready signal and spaces the input data samples the correct number of cycles apart. You do not have to change your Input Stimulus settings for this implementation.

After you generate HDL code, you can see the updated resource estimate on the Resources tab. This implementation uses only one multiplier but has slower throughput than the parallel filter because samples can be applied only every 13 cycles. The single multiplier is shared in time between the symmetry-optimized coefficients.

Using the app you can explore hardware implementations of algorithms without constructing a model or script to run the algorithm. You can quickly generate HDL code and testbench components for your algorithms, and assess the hardware resource use of your IP block.

The export_progCICDecim_tb.m file contains code that assigns the stimulus values from the Input Stimulus block in the app, and code that calls the System object to simulate the algorithm. You can modify the _tb file to apply other input values, and analyze the output data.

%Testbench generated using HDL IP Designer
%
% generate input stimulus for DUT
fs = 44.1e3; % Original sampling frequency: 44.1 kHz
n = (0:1023); % 1024 samples
x = fi(sin(2*pi*1e3/fs*n),true,16,8);
testbench.data = reshape(x,size(x,2),size(x,1));
data = testbench.data ;

% R value must be scalar
testbench.R = fi(2,0,12,0);
R = testbench.R ;
R = repmat(testbench.R,1024,1);

NumDim = length(size(data));
NumSamples = size(data,1);
SamplesPerFrame = 1;
NumChannels = size(data,2);

valid = true(1,NumSamples);
dataIn = data;
validIn = valid;
RIn = R;
 
% call DUT with stimulus and save output
for ii = 1:1:NumSamples
   [dataOut(ii), validOut(ii)] = export_progCICDecim(dataIn(ii), validIn(ii), RIn(ii));
end
    

For instance, in export_progCICDecim_tbEx.m, this example sets the R input to change every 265 input samples.

  testbench.R = fi([2,4,8,2],0,12,0);
  R = [repmat(testbench.R(1),256,1);repmat(testbench.R(2),256,1);repmat(testbench.R(3),256,1);repmat(testbench.R(4),256,1)];

Run export_progCICDecim_tbEx.m and display the results of simulating the System object with the new R values by using the dsp.LogicAnalyzer object. In the waveform, you can see the changing R value and the effect on the output valid pattern after decimation.

export_progCICDecim_tbEx
analyzer = dsp.LogicAnalyzer( ...
    'Name', 'CIC Decim Waveform', ...
    'NumInputPorts', 5, ...
    'DisplayChannelRadix', 'Hexadecimal', ...
    'SampleTime', 1, ...
    'TimeSpan',1024);
modifyDisplayChannel(analyzer, 1, 'Name', 'dataIn');
modifyDisplayChannel(analyzer, 2, 'Name', 'validIn');
modifyDisplayChannel(analyzer, 3, 'Name', 'R');
modifyDisplayChannel(analyzer, 4, 'Name', 'dataOut');
modifyDisplayChannel(analyzer, 5, 'Name', 'validOut');
analyzer(dataIn, validIn', RIn, dataOut', validOut');

This example shows how to configure a programmable CIC Interpolator algorithm in the DSP HDL IP Designer app, and export the design and input stimulus as a Simulink® model.

This example includes a MAT file that loads the algorithm and HDL code generation settings into the app. It also includes the exported Simulink model file.

Open the DSP HDL IP Designer app and click Open Session. Load the app-cicinterp-ex.mat file. The file configures a CIC Interpolator algorithm with the Interpolator factor source parameter set to Input port and the largest expected interpolation factor, Interpolation factor (Rmax) parameter, set to 12. In this configuration, the algorithm has an input port R for the interpolation factor, and accepts and returns scalar data samples. Because interpolation requires more output cycles than input cycles, the algorithm also has a backpressure signal, ready, that indicates when the algorithm is ready to accept new input samples.

Click the Input Stimulus block to see the default values for the input. The input interpolation factor must be data type fixdt(0,12,0) and must be an integer in the range from 1 to the Interpolation factor (Rmax) value. In Input Stimulus, the testbench.R value must be a scalar. This value represents the dimension and data type of the input. The testbench.data value represents the dimensions and data type of the input samples, and specifies how many samples to apply over time in the testbench.

In the toolbar, click Export > Export to Simulink. The app opens a Simulink model that contains a CIC Interpolator block configured with the same settings as the algorithm in the app.

open_system(export_progCICInterp)

The InitFcn callback of the model assigns the input stimulus to workspace variables, and creates values for input control signals. To view and edit the InitFcn callback, from the Model Settings drop-down menu, open Model Properties and select the Callbacks tab.

  %Testbench generated using HDL IP Designer

% generate input stimulus for DUT
fs = 22.05e3; % Original sampling frequency: 22.05 kHz
n = (0:511); % 512 samples
x = fi(sin(2*pi*1e3/fs*n),true,16,8)';
testbench.data = x;
data = testbench.data ;

% R value must be scalar
testbench.R = fi(2,0,12,0);
R = testbench.R ;
R = repmat(testbench.R,512,1);

NumDim = length(size(data));
NumSamples = size(data,1);
SamplesPerFrame = 1;
NumChannels = size(data,2);

valid = true(1,NumSamples);
dataIn = data;
validIn = valid;
RIn = R;
simTime = NumSamples+100;

The exported model is configured to capture the input and output signals of your algorithm to the Logic Analyzer waveform viewer. You can modify the model to apply other input values, or analyze the output data.

For instance, in export_progCICDecim.slx, this example sets the input interpolation factor, R, to a different value every 128 input samples. Because the backpressure signal slows the input rate for larger interpolation factors, the example modifies the simTime setting of the model to allow time to apply all 512 input samples.

testbench.R = fi([2,4,8,2],0,12,0);
R = [repmat(testbench.R(1),256,1);repmat(testbench.R(2),256,1);repmat(testbench.R(3),256,1);repmat(testbench.R(4),256,1)];
...
simTime = NumSamples*4;

Run export_progCICInterp.slx and observe the results of simulating the block with the new R values in the Logic Analyzer. You can see the changing R value and the effect on the backpressure signal and output valid pattern after interpolation.