eq, ==

Determine whether real-world values are equal

Syntax

A == B

eq(A,B)

Description

A == B returns a logical array with elements set to logical 1 (true) where the real-world values of arrays A and B are equal, when A or B is a fi object. Otherwise, the element is logical 0 (false). The test compares both real and imaginary parts of numeric arrays.

In relational operations comparing a floating-point value to a fixed-point value, the floating-point value is cast to a fixed-point type that preserves the relative order of the value with respect to the value in the fixed-point fi object.

example

eq(A,B) is an alternate way to execute A == B, but is rarely used.

example

Examples

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Compare Two `fi` Objects

Open Live Script

Use the eq function to determine if two fi objects have the same real-world value.

a = fi(pi);
b = fi(pi,1,32);
a == b

ans = logical
   0

Input a has a 16-bit word length, while input b has a 32-bit word length. The eq function returns 0 because the two fi objects do not have the same real-world value.

Compare a Double to a `fi` Object

Open Live Script

When comparing a double to a fi object, the floating-point double is cast to a type that preserves the relative order of the value with respect to the value in the fixed-point fi object. This behavior allows relational operations to work between fi objects and floating-point constants without introducing floating-point values in generated code.

a = fi(pi);
b = pi;
eq(a,b)

ans = logical
   0

Input Arguments

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`A,B` — Operands
scalars | vectors | matrices | multidimensional arrays

Operands, specified as scalars, vectors, matrices, or multidimensional arrays. Inputs A and B must either be the same size or have sizes that are compatible. For more information, see Compatible Array Sizes for Basic Operations.

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using MATLAB® Coder™.

Usage notes and limitations:

Fixed-point signals with different biases are not supported.

HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

Version History

Introduced before R2006a

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R2022a: Implicit expansion change affects arguments for operators

Starting in R2022a with the addition of implicit expansion for fi eq, some combinations of arguments for basic operations that previously returned errors now produce results.

If your code uses element-wise operators and relies on the errors that MATLAB^® previously returned for mismatched sizes, particularly within a try/catch block, then your code might no longer catch those errors.

For more information on the required input sizes for basic array operations, see Compatible Array Sizes for Basic Operations.

R2022a: Improved accuracy in comparing `fi` objects and floating-point numbers using relational operators

In previous releases, when comparing a single or double to a fi object, the floating-point value was cast to the same word length and signedness of the fi object. This could lead to incorrect results. For example,

fi(0,0,8) > [-1,10]

ans =

  1×2 logical array

   0   0

fi(65534)
fi(65534.25) == 65534.25

ans = 

       65534

          DataTypeMode: Fixed-point: binary point scaling
            Signedness: Signed
            WordLength: 16
        FractionLength: -1

ans =

  logical

   1

Starting in R2022a, relational operators comparing fi objects to floating-point numbers will always return the mathematically correct behavior. The previous examples now gives these results:

fi(0,0,8) > [-1,10]

ans =

  1×2 logical array

   1   0

Note that the updated algorithm may produce subtle, but accurate, results. For example:

fi(pi) == pi

ans =

  logical

   0

Simulation results for relational operations between fi objects and floating-point singles or doubles may be more accurate than in previous releases. The updated algorithm requires a modest wordlength growth of 3 bits or fewer, which may lead to slight changes in efficiency in simulation.

eq, ==

Syntax

Description

Examples

Compare Two fi Objects

Compare a Double to a fi Object

Input Arguments

A,B — Operands scalars | vectors | matrices | multidimensional arrays

Extended Capabilities

C/C++ Code Generation Generate C and C++ code using MATLAB® Coder™.

HDL Code Generation Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.