FPGA 在环仿真

R2026b
使用 FPGA 硬件进行验证

运行与在 Microchip 板上运行的 HDL 设计同步的 Simulink® 或 MATLAB® 仿真。

App

FPGA 在环向导Generate an FPGA-in-the-loop (FIL) block or System object from existing HDL files
逻辑分析仪Visualize, measure, and analyze transitions and states over time

函数

filProgramFPGALoad programming file onto FPGA
programFPGA Load programming file associated with FILSimulation or FILFreeRunning system object onto FPGA

对象

hdlverifier.FILSimulation FIL simulation with MATLAB

模块

FIL Simulation blockFIL SimulationSimulate HDL code on FPGA hardware from Simulink

主题

  • FPGA-in-the-Loop Simulation

    FPGA-in-the-loop (FIL) simulation provides the capability to use Simulink or MATLAB software for testing designs in real hardware for any existing HDL code.

  • FPGA-in-the-Loop Simulation Workflows

    Choose between generating a block or System object™, and decide whether to use the FIL Wizard or HDL Workflow Advisor.

精选示例

Verify HDL Implementation of PID Controller Using FPGA-in-the-Loop for Altera and Microchip Devices

Verify HDL Implementation of PID Controller Using FPGA-in-the-Loop for Altera and Microchip Devices

Set up an FPGA-in-the-Loop (FIL) application using HDL Coder™.