为 MATLAB 加权混合算法生成 SystemVerilog 代码

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此示例说明如何从实现两个图像加权混合的 MATLAB® 函数生成可综合的 SystemVerilog HDL 代码。当您生成 SystemVerilog 而不是 Verilog® 时，代码生成器会生成数组端口和包声明，从而提高生成代码的可读性。

检查加权混合算法和测试平台

在图像处理流水线中，像素以小图块形式进行处理。函数 systemverilog_example.m 实现一个加权混合算法，该算法对 uint8 类型的两个 2×2 矩阵（对应于 2×2 像素图块）执行按元素加权混合。该函数将输入转换为 uint32 以进行中间计算，从而避免在乘法和累加期间发生溢出。

type systemverilog_example.m

function out = systemverilog_example(in1, in2, alpha, beta)

a = uint32(alpha);
b = uint32(beta);

x = uint32(in1);
y = uint32(in2);

accumulate = a .* x + b .* y + uint32(128);

rescale = floor(accumulate/256);

z = min(rescale, uint32(255));

out = uint8(z);

end

测试平台 systemverilog_example_tb.m 通过构建两个不同的 8×8 测试图像、以 2×2 图块处理这两个图像并将结果与全精度 MATLAB 参考进行比较，来测试加权混合算法。为了处理图块，测试平台将 2×2 数组输入直接传递给函数。这种基于数组的接口在生成的 SystemVerilog 代码中映射到数组端口。

coder.example.extractLines("systemverilog_example_tb.m","in1Blk","beta);",1,1)

        in1Blk = image1(r:r+1, c:c+1);
        in2Blk = image2(r:r+1, c:c+1);

        outBlk = systemverilog_example(in1Blk, in2Blk, alpha, beta);

使用不同混合权重测试算法

使用 50/50 加权混合运行测试平台。变量 alpha 和 beta 控制每个输入图像对输出的贡献量。当 alpha 和 beta 各等于 128 时，输出是两个图像的等量混合。

alpha = uint8(128);
beta = uint8(128);
systemverilog_example_tb

figure(2)
tiledlayout
nexttile
imshow(weightedImage)

将 alpha 设置为 25，将 beta 设置为 231，以使输出权重偏向第二个图像。如果 alpha 和 beta 存在，测试平台会从工作区读取它们。

alpha = uint8(25);
beta = uint8(231);
systemverilog_example_tb
nexttile
imshow(weightedImage)

使用 MATLAB 命令行生成 SystemVerilog 代码

要从 MATLAB 函数生成 SystemVerilog 代码，请创建配置对象，以指定用于验证的测试平台和用于代码生成的目标语言。

创建一个 coder.FixPtConfig 配置对象，并将 TestBenchName 属性设置为 "systemverilog_example_tb"。

fixptcfg = coder.config("fixpt");
fixptcfg.TestBenchName = "systemverilog_example_tb";

创建一个 coder.HdlConfig 对象，并将 TestBenchName 属性设置为 "systemverilog_example_tb"。

hdlcfg = coder.config("hdl");
hdlcfg.TestBenchName = "systemverilog_example_tb";

要生成 SystemVerilog 而不是 Verilog，请将 TargetLanguage 属性设置为 "SystemVerilog"。

hdlcfg.TargetLanguage = "SystemVerilog";

使用 codegen 命令生成 HDL 代码。使用 -float2fixed 指定定点配置，使用 -config 指定 HDL 配置，并指定入口函数名称。

codegen -float2fixed fixptcfg -config hdlcfg systemverilog_example

===================================================
Design Name: <a href="matlab:edit('/tmp/Bdoc26b_3351752_3509937/tpb460897c/hdlcoder-ex49202891/systemverilog_example.m')">systemverilog_example</a>
Test Bench Name: <a href="matlab:edit('/tmp/Bdoc26b_3351752_3509937/tpb460897c/hdlcoder-ex49202891/systemverilog_example_tb.m')">systemverilog_example_tb</a>
===================================================

Input types not specified for design(s) 'systemverilog_example', inferring types by simulating the first test bench: 'systemverilog_example_tb' in the base workspace.

============= Step1: Analyze Floating-Point Code ==============

Code generation successful.


============= Step1a: Verify Floating-Point Code ==============

### Analyzing the design 'systemverilog_example'
### Analyzing the test bench(es) 'systemverilog_example_tb'
### Begin Floating-Point Simulation (Instrumented)
### Floating-Point Simulation Completed in   2.2007 sec(s)
### Elapsed Time:             3.0022 sec(s)

============= Step2: Propose Types Based on Range Information ==============


============= Step3: Generate Fixed-Point Code ==============

### Generating Fixed-Point MATLAB Code <a href="matlab:edit('/tmp/Bdoc26b_3351752_3509937/tpb460897c/hdlcoder-ex49202891/codegen/systemverilog_example/fixpt/systemverilog_example_fixpt.m')">systemverilog_example_fixpt</a> Using Proposed Types
### Generating Fixed-Point MATLAB Design Wrapper <a href="matlab:edit('/tmp/Bdoc26b_3351752_3509937/tpb460897c/hdlcoder-ex49202891/codegen/systemverilog_example/fixpt/systemverilog_example_wrapper_fixpt.m')">systemverilog_example_wrapper_fixpt</a>
### Generating Mex file for ' systemverilog_example_wrapper_fixpt '
Code generation successful: <a href="matlab: emlcprivate('emcOpenReport','/tmp/Bdoc26b_3351752_3509937/tpb460897c/hdlcoder-ex49202891/codegen/systemverilog_example/fixpt/reports/systemverilog_example_wrapper_fixpt_mex/html/report.mldatx');">View report</a>
### Generating Type Proposal Report for 'systemverilog_example' <a href="matlab:web('/tmp/Bdoc26b_3351752_3509937/tpb460897c/hdlcoder-ex49202891/codegen/systemverilog_example/fixpt/systemverilog_example_report.html', '-new')">systemverilog_example_report.html</a>

===================================================
Code generation successful.
### Begin MATLAB to HDL Code Generation...
### Working on DUT: systemverilog_example_fixpt.
### Using TestBench: systemverilog_example_tb.
### Begin SystemVerilog Code Generation
### Working on systemverilog_example_fixpt as <a href="matlab:edit('/tmp/Bdoc26b_3351752_3509937/tpb460897c/hdlcoder-ex49202891/codegen/systemverilog_example/hdlsrc/systemverilog_example_fixpt.sv')">systemverilog_example_fixpt.sv</a>.
### Generating package file <a href="matlab:edit('/tmp/Bdoc26b_3351752_3509937/tpb460897c/hdlcoder-ex49202891/codegen/systemverilog_example/hdlsrc/systemverilog_example_fixpt_pkg.sv')">systemverilog_example_fixpt_pkg.sv</a>.
### Generating Resource Utilization Report <a href="matlab:hdlcoder.report.openDdg('/tmp/Bdoc26b_3351752_3509937/tpb460897c/hdlcoder-ex49202891/codegen/systemverilog_example/hdlsrc/resource_report.html')">resource_report.html</a>.
### Generating Optimization report  
### To rerun codegen evaluate the following commands...

---------------------
cgi    = load('/tmp/Bdoc26b_3351752_3509937/tpb460897c/hdlcoder-ex49202891/codegen/systemverilog_example/hdlsrc/codegen_info.mat');
cfg    = cgi.CodeGenInfo.codegenSettings;
fxpCfg = cgi.CodeGenInfo.fxpCfg;
codegen -float2fixed fxpCfg -config cfg -report
---------------------

### Generating HDL Conformance Report <a href="matlab:web('/tmp/Bdoc26b_3351752_3509937/tpb460897c/hdlcoder-ex49202891/codegen/systemverilog_example/hdlsrc/systemverilog_example_fixpt_hdl_conformance_report.html')">systemverilog_example_fixpt_hdl_conformance_report.html</a>.
### HDL Conformance check complete with 0 errors, 0 warnings, and 0 messages.
### Code generation successful: To view the report, open('codegen/systemverilog_example/hdlsrc/html/report.mldatx')

检查生成的 SystemVerilog 代码

代码生成器生成两个 SystemVerilog 文件：一个包含共享类型定义的包文件，以及一个在接口处使用数组端口的设计模块。在测设备 (DUT) 是顶层设计模块。

查看包文件中的共享类型定义。代码生成器为 MATLAB 函数中使用的每个唯一数据类型创建一个 typedef。

file = fullfile("codegen","systemverilog_example","hdlsrc","systemverilog_example_fixpt_pkg.sv");
coder.example.extractLines(file,"package systemverilog_example_fixpt_pkg;","endpackage: systemverilog_example_fixpt_pkg",1,1)

package systemverilog_example_fixpt_pkg;
  typedef  logic  [7:0] vector_of_unsigned_logic_8;
  typedef  logic  [31:0] vector_of_unsigned_logic_32;
  typedef  logic  [23:0] vector_of_unsigned_logic_24;
  typedef  logic  [15:0] vector_of_unsigned_logic_16;
  typedef  logic  [16:0] vector_of_unsigned_logic_17;
  typedef  logic  [32:0] vector_of_unsigned_logic_33;
endpackage: systemverilog_example_fixpt_pkg

查看 DUT 模块中的包导入和数组端口。MATLAB 函数中的 2×2 数组输入 in1 和 in2 映射到数组端口，从而在 HDL 接口处保留图块形状。

file = fullfile("codegen","systemverilog_example","hdlsrc","systemverilog_example_fixpt.sv");
coder.example.extractLines(file,"import systemverilog_example_fixpt_pkg::* ;",");",1,1)

          import systemverilog_example_fixpt_pkg::* ;
          (  input vector_of_unsigned_logic_8 in1[0:1] [0:1]  /* ufix8 [2x2] */,
             input vector_of_unsigned_logic_8 in2[0:1] [0:1]  /* ufix8 [2x2] */,
             input logic [7:0] alpha  /* ufix8 */,
             input logic [7:0] beta  /* ufix8 */,
             output vector_of_unsigned_logic_8 out[0:1] [0:1]  /* ufix8 [2x2] */);

与生成的 Verilog 代码进行比较

要了解 SystemVerilog 的优势，请为同一设计生成 Verilog 代码并比较接口。

hdlcfg.TargetLanguage = "Verilog";
codegen -float2fixed fixptcfg -config hdlcfg systemverilog_example

===================================================
Design Name: <a href="matlab:edit('/tmp/Bdoc26b_3351752_3509937/tpb460897c/hdlcoder-ex49202891/systemverilog_example.m')">systemverilog_example</a>
Test Bench Name: <a href="matlab:edit('/tmp/Bdoc26b_3351752_3509937/tpb460897c/hdlcoder-ex49202891/systemverilog_example_tb.m')">systemverilog_example_tb</a>
===================================================

Input types not specified for design(s) 'systemverilog_example', inferring types by simulating the first test bench: 'systemverilog_example_tb' in the base workspace.

============= Step1: Analyze Floating-Point Code ==============


============= Step1a: Verify Floating-Point Code ==============

### Analyzing the design 'systemverilog_example'
### Analyzing the test bench(es) 'systemverilog_example_tb'
### Begin Floating-Point Simulation (Instrumented)
### Floating-Point Simulation Completed in   1.2391 sec(s)
### Elapsed Time:             1.9078 sec(s)

============= Step2: Propose Types Based on Range Information ==============


============= Step3: Generate Fixed-Point Code ==============

### Generating Fixed-Point MATLAB Code <a href="matlab:edit('/tmp/Bdoc26b_3351752_3509937/tpb460897c/hdlcoder-ex49202891/codegen/systemverilog_example/fixpt/systemverilog_example_fixpt.m')">systemverilog_example_fixpt</a> Using Proposed Types
### Generating Fixed-Point MATLAB Design Wrapper <a href="matlab:edit('/tmp/Bdoc26b_3351752_3509937/tpb460897c/hdlcoder-ex49202891/codegen/systemverilog_example/fixpt/systemverilog_example_wrapper_fixpt.m')">systemverilog_example_wrapper_fixpt</a>
### Generating Mex file for ' systemverilog_example_wrapper_fixpt '
Code generation successful: <a href="matlab: emlcprivate('emcOpenReport','/tmp/Bdoc26b_3351752_3509937/tpb460897c/hdlcoder-ex49202891/codegen/systemverilog_example/fixpt/reports/systemverilog_example_wrapper_fixpt_mex/html/report.mldatx');">View report</a>
### Generating Type Proposal Report for 'systemverilog_example' <a href="matlab:web('/tmp/Bdoc26b_3351752_3509937/tpb460897c/hdlcoder-ex49202891/codegen/systemverilog_example/fixpt/systemverilog_example_report.html', '-new')">systemverilog_example_report.html</a>

===================================================
Code generation successful.
### Begin MATLAB to HDL Code Generation...
### Working on DUT: systemverilog_example_fixpt.
### Using TestBench: systemverilog_example_tb.
### Begin Verilog Code Generation
### Working on systemverilog_example_fixpt as <a href="matlab:edit('/tmp/Bdoc26b_3351752_3509937/tpb460897c/hdlcoder-ex49202891/codegen/systemverilog_example/hdlsrc/systemverilog_example_fixpt.v')">systemverilog_example_fixpt.v</a>.
### Generating Resource Utilization Report <a href="matlab:hdlcoder.report.openDdg('/tmp/Bdoc26b_3351752_3509937/tpb460897c/hdlcoder-ex49202891/codegen/systemverilog_example/hdlsrc/resource_report.html')">resource_report.html</a>.
### Generating Optimization report  
### To rerun codegen evaluate the following commands...

---------------------
cgi    = load('/tmp/Bdoc26b_3351752_3509937/tpb460897c/hdlcoder-ex49202891/codegen/systemverilog_example/hdlsrc/codegen_info.mat');
cfg    = cgi.CodeGenInfo.codegenSettings;
fxpCfg = cgi.CodeGenInfo.fxpCfg;
codegen -float2fixed fxpCfg -config cfg -report
---------------------

### Generating HDL Conformance Report <a href="matlab:web('/tmp/Bdoc26b_3351752_3509937/tpb460897c/hdlcoder-ex49202891/codegen/systemverilog_example/hdlsrc/systemverilog_example_fixpt_hdl_conformance_report.html')">systemverilog_example_fixpt_hdl_conformance_report.html</a>.
### HDL Conformance check complete with 0 errors, 0 warnings, and 0 messages.
### Code generation successful: To view the report, open('codegen/systemverilog_example/hdlsrc/html/report.mldatx')

查看生成的 Verilog 文件中的 DUT 端口。如果不使用 SystemVerilog，代码生成器会将 2×2 数组输入展平为各个标量端口，并且不会为共享类型定义生成包文件。

file = fullfile("codegen","systemverilog_example","hdlsrc","systemverilog_example_fixpt.v");
coder.example.extractLines(file,"module systemverilog_example_fixpt",");",1,1)

module systemverilog_example_fixpt
          (in1_0,
           in1_1,
           in1_2,
           in1_3,
           in2_0,
           in2_1,
           in2_2,
           in2_3,
           alpha,
           beta,
           out_0,
           out_1,
           out_2,
           out_3);

要进一步针对目标速度和面积约束优化设计，请参阅Introduction to Optimizations in HDL Coder。

另请参阅

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