为 AXI4 接口设计模型
通过使用简化协议映射到 AXI4-Stream、AXI4-Stream 视频或 AXI4 主接口，在 Simulink® 中进行算法建模
使用 HDL Coder™ 软件，您可以在模型中实现简化协议以映射到 AXI4-Stream、AXI4-Slave 或 AXI4 Master。该软件生成具有对应接口的 HDL IP 核。
主题
- Model Design for AXI4 Slave Interface Generation
How to design your model for AXI4 or AXI4-Lite interfaces for scalar, vector ports, bus data types, and read back values.
- Model Design for AXI4-Stream Interface Generation
How to design your model for AXI4-Stream vector or scalar interface generation.
- Model Design for AXI4 Master Interface Generation
Description of AXI4 Master protocol, and how you can design your model for IP core generation with AXI4-Master interfaces.
