Bit Reduce

AND, OR, or XOR bit reduction on all input signal bits to single bit

Libraries:
HDL Coder / Logic and Bit Operations

Description

The Bit Reduce block performs a selected bit-reduction operation (AND, OR, or XOR) on all the bits of the input signal, for a single-bit result.

Ports

Input

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Port_1 — Input Signal
scalar | vector

Input signal on which the bit-reduction operation is performed.

Minimum bit width: 2
Maximum bit width: 128

Output

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Port_1 — Output Signal
scalar | vector

Output signal that is bit-reduced.

Data Types: ufix1

Parameters

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Reduction Mode — Reduction operation on input
`AND` (default) | `OR` | `XOR`

Specifies the reduction operation:

AND (default): Perform a bitwise AND reduction of the input signal.
OR: Perform a bitwise OR reduction of the input signal.
XOR: Perform a bitwise XOR reduction of the input signal.

Programmatic Use

Block parameter: mode

Type: string scalar | character vector

Value: "AND" | "OR" | "XOR"

Default: 'AND'

Extended Capabilities

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C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has one default HDL architecture.

HDL Block Properties

General
ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is `0`. For more details, see ConstrainedOutputPipeline.
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see InputPipeline.
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see OutputPipeline.
SynthesisAttributes	Specifies the synthesis attributes for the blocks and block output signals in the model. The generated HDL code contains these attributes. For more information, see SynthesisAttributes.

Version History

Introduced in R2014a

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R2026a: Specify synthesis attributes for blocks and block output signals

Use the SynthesisAttributes HDL block property to specify the synthesis attributes for the block and its output signals. HDL Coder includes these attributes in the generated HDL code.

Bit Reduce

Description

Ports

Input

Port_1 — Input Signal
scalar | vector

Output

Port_1 — Output Signal
scalar | vector

Parameters

Reduction Mode — Reduction operation on input
`AND` (default) | `OR` | `XOR`

Programmatic Use

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

Version History

R2026a: Specify synthesis attributes for blocks and block output signals

See Also

Blocks

Bit Reduce

Description

Ports

Input

Port_1 — Input Signal scalar | vector

Output

Port_1 — Output Signal scalar | vector

Parameters

Reduction Mode — Reduction operation on input AND (default) | OR | XOR

Programmatic Use

Extended Capabilities

C/C++ Code Generation Generate C and C++ code using Simulink® Coder™.

HDL Code Generation Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

Version History

R2026a: Specify synthesis attributes for blocks and block output signals

See Also

Blocks

Port_1 — Input Signal
scalar | vector

Port_1 — Output Signal
scalar | vector

Reduction Mode — Reduction operation on input
`AND` (default) | `OR` | `XOR`

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.