Supported Synthesizable RTL Constructs and keywords in HDL Coder

The table lists the synthesizable VHDL^® constructs in HDL Coder™.

Entity and Architecture Declaration

Package and Library Declaration

Component and Configuration Declaration

VHDL Constructs	Supported?	Comments
Configuration declaration	No	–
Configuration specification	No	–
Component declaration	Yes	–
Component instantiation	Yes	Supports ordered or named port map. Mixed and generic port mapping is not supported.
Generic clause	Yes	–

Data Types and Vectors

VHDL Constructs	Supported?	Comments
Integer declaration	Yes	–
Real declaration	No	–
String declaration	No	–
Bit_vector	Yes	–
Enumerated	Yes	–
Std_logic	Yes	Values other than 0 and 1 (U, X, Z, W, L, H) are not supported.
Vector declaration	Yes	–

Identifiers and Comments

VHDL Constructs	Supported?	Comments
Numbers (based, normal)	Yes	Based literals support bases 2, 8, 10, and 16.
Identifiers	Yes	–
Standard package functions	Yes	Supports signed, unsigned, to_std_logic_vector, resize, and to_integer.
Attribute instances	No	–
Attribute declaration	No	–
Records	No	–
Comments	Yes	–

Assignments

VHDL Constructs	Supported?	Comments
Assignment statements (signal, variable)	Yes	–
Selected signal assignment	Yes	–

Operators

VHDL Constructs	Supported?	Comments
Arithmetic operators (+,-,*, mod, rem)	Yes	–
Relational operators (<, >, <<. >>)	Yes	–
Unary operators (+,-)	Yes	–
Logical operators (and, or, xor, nand, and nor)	Yes	–
Absolute and exponential operators (abs, **)	Yes	–
Gates	Yes	–

Conditional and Looping Statements

Process Statements and Procedure Definitions

VHDL Constructs	Supported?	Comments
Process statement	Yes	–
Functions	No	–
Blocks	No	–
Procedure definitions	No	–
Function calls	Yes	Recursive function calls are not supported.

Event Control Statements

The table lists the supported synthesizable Verilog^® constructs in HDL Coder.

Module Definition and Instantiation

Verilog Constructs	Supported?	Comments
Library declaration	No	–
Configuration declaration	No	–
Module declaration	Yes	–
Module parameter port list	Yes	–
Port declarations	Yes	–
Module without ports	No	–
Local parameter declaration	Yes	–
Parameter declaration	Yes	--
Module instatiation	Yes	--

Data Types and Vectors

Verilog Constructs	Supported?	Comments
Net declaration (Wire, Supply0, Supply1)	Yes	–
Reg declaration	Yes	–
Integer declaration	Yes	–
Real declaration	No	–
String declaration	No	–
Vector declaration	Yes	–
Array support	Yes	Array indexing and multidimensional arrays are not supported.

Identifiers and Comments

Verilog Constructs	Supported?	Comments
Lexical tokens (Whitespace, operator, comment)	Yes	–
Numbers (Decimal, Binary, Hexadecimal, and Octal)	Yes	Does not support numbers such as `x` and `z`.
Identifiers (Simple, Escaped)	No	–
Compiler directives (`define,`undef, `ifndef, `else if)	Yes	–
System Functions ($signed, $unsigned)	Yes	–
Attribute instances	No	–
Comments	No	–

Assignments

Verilog Constructs	Supported?	Comments
Continuous assignment	Yes	–
Procedural assignment (Always block)	Yes	–
Blocking assignment	Yes	–
Non-blocking assignment	Yes	–

Operators

Conditional and Looping Statements

Verilog Constructs	Supported?	Comments
If-else statement	Yes	–
Case statement	Yes	–
Conditional operators (?:)	Yes	–
For loop	No	–
Loop Generate construct	No	–
Conditional Generate construct	No	–
Generate region	No	–
Genvar declaration	No	–

Procedural Blocks and Events

Verilog Constructs	Supported?	Comments
Initial construct (ROM modeling)	No	–
Always construct	Yes	–
Task declaration	No	–
Function declaration	No	–
Sequential blocks	Yes	–
Block declarations	Yes	–
Event control statements	Yes	–
Function calls	Yes	Does not supports recursive function calls.
Task enable	No	–

Others

Verilog Constructs	Supported?	Comments
Gate instantiation	No	–
Drive strength	No	–
Delays	No	–
Specparams	No	–
Specify block	No	–
Semantic verification (unused ports, correct module instantiation)	Yes	–
Clock bundle identification	Yes	Multiple sample rates and multiple clock signals are not supported.
Register inference	Yes	–
RAM inference	Yes	Supports Simple Dual Port RAM. Other types of RAM are not supported.
ROM inference	No	–
Counter inference	No	–

The table lists the supported synthesizable VHDL keywords in HDL Coder.

The table lists the supported synthesizable Verilog keywords supported in HDL Coder.