Check clock, reset, and enable signals

Check ID: com.mathworks.HDL.ModelChecker.runClockResetEnableChecks

Check ID: com.mathworks.HDL.ModelAdvisor.runClockResetEnableChecks

Check naming convention for clock, reset, and enable signals.

Available with Simulink^® and HDL Coder™.

Description

This check verifies whether clock, reset, and clock enable signals follow the recommended naming convention. Clock signal names must contain clk or ck, reset signal names must contain rstx, resetx, rst_n, reset_n, rst_x, or reset_x, and clock enable signal names must contain en. This check corresponds to rule 1.A.E.2 of the industry-standard rules.

Results and Recommended Actions

To fix this warning, click Modify Settings and the code generator updates the clock, reset, and enable signals to adhere to the naming conventions.