By default, HDL Coder™ does not perform CSD or FCSD optimizations. Code generated for the Gain block retains multiplier operations.

When you specify this option, the generated code decreases the area used by the model while maintaining or increasing clock speed, using canonical signed digit (CSD) techniques. CSD replaces multiplier operations with add and subtract operations.

CSD minimizes the number of addition operations required for constant multiplication by representing binary numbers with a minimum count of nonzero digits.

This option uses factored CSD (FCSD) techniques, which replace multiplier operations with shift and add/subtract operations on certain factors of the operands. These factors are generally prime but can also be a number close to a power of 2, which favors area reduction.

This option lets you achieve a greater area reduction than CSD, at the cost of decreasing clock speed.

When you specify this option, HDL Coder chooses between the CSD or FCSD optimizations. The coder chooses the optimization that yields the most area-efficient implementation, based on the number of adders required.

HDL Coder does not use multipliers, unless conditions are such that CSD or FCSD optimizations are not possible (for example, if the design uses floating-point arithmetic).