Map Persistent Arrays to RAM
To map persistent array variables to RAMs in the generated High-Level Synthesis (HLS) code, use the RAM mapping optimization. Without this optimization, the code generator maps the array variables to registers. RAM mapping is an area optimization that reduces the area of your design in the target hardware.
Enable RAM Mapping
In the HDL Workflow Advisor, select the HLS Code Generation node, and then select the Optimizations tab.
Select Map persistent array variables to RAMs.
Set RAM mapping threshold to the size (in bits) of the smallest persistent array that you want to map to RAM.
This table shows the RAM mapping behavior for persistent arrays when using the Map persistent array variables to RAMs parameter.
Parameter Setting | Mapping Behavior |
---|---|
on | Map to RAM in the generated HLS code. |
off | Map to registers in the generated HLS code. |
Additional Notes
The large persistent arrays whose size in bits is greater than or equal to RAM mapping threshold are mapped to RAM. The size in bits is calculated as
NumElements
*WordLength
, where:NumElements
is the number of elements in the array.WordLength
is the number of bits that represent the data type of the array.
The list of RAM variables is stored in the
ml.tcl
metadata file generated during HLS code generation. This metadata file is read by the Stratus HLS tool during project creation and maps these variables to RAM.If Initialize Block RAM is cleared, the RAM variables that an initial value of zero are not initialized inside the
initialize_ram_vars()
method.If the initial value of the variables is nonzero, then those RAM variables are initialized inside the
initialize_ram_vars()
method, irrespective of the Initialize Block RAM value.When you set the synthesis tool to
Xilinx Vitis HLS
, the Map persistent array variables to RAMs parameter and any related settings become irrelevant. The tool automatically selects appropriate memory types for arrays in the generated HLS code during synthesis.