Supported SystemVerilog Constructs for HDL Import
R2026bUse the importhdl
function to import synthesizable SystemVerilog code into the Simulink® modeling environment. Make sure that the constructs used in the HDL code are
supported by the importhdl function.
The following tables list the supported SystemVerilog constructs that you can use when you import your HDL code. If you use an
unsupported construct, the importhdl function generates an error when
parsing the input HDL file. SystemVerilog HDL import can sometimes ignore the presence of certain constructs in the HDL
code. To learn more, see the Comments column in the
table.
Supported Verilog Constructs
When you import SystemVerilog files, the importhdl function also supports all supported
Verilog® constructs. You can use these constructs inside SystemVerilog files without modification. For more information about supported Verilog constructs for HDL import, see Supported Verilog Constructs for HDL Import.
The following tables describe additional SystemVerilog language features that HDL import supports beyond those documented in Supported Verilog Constructs for HDL Import.
Procedural Blocks and Subprograms
| SystemVerilog Constructs | Supported? | Comments |
|---|---|---|
always_comb | Yes | – |
always_ff | Yes | – |
always_latch | No | – |
| Function declaration | Yes | Supports SystemVerilog function syntax with typed arguments, explicit return types, and
SystemVerilog data types such as logic, bit,
byte, shortint, int, and
longint. |
Data Types and Type Definitions
| SystemVerilog Constructs | Supported? | Comments |
|---|---|---|
logic | Yes | Supports only 0 and 1 values. Unknown
(X) and high-impedance (Z) values are not
supported. |
bit | Yes | – |
byte | Yes | – |
shortint | Yes | – |
int | Yes | – |
longint | Yes | – |
real | No | – |
shortreal | No | – |
| Packed arrays | Yes | Supports one-dimensional packed arrays only. Multidimensional packed arrays are not supported. |
| Unpacked arrays | No | – |
enum | No | – |
typedef | No | – |
struct | No | – |
union | No | – |
Case Statement Qualifiers
| SystemVerilog Constructs | Supported? | Comments |
|---|---|---|
unique | Yes | Ignored |
unique0 | Yes | Ignored |
priority | Yes | Ignored |
Package Declarations
| SystemVerilog Constructs | Supported? | Comments |
|---|---|---|
| Package declaration | No | – |
| Package import declaration | No | – |
Parameters and Constants
| SystemVerilog Constructs | Supported? | Comments |
|---|---|---|
| Typed parameter declaration | Yes | Supports parameters declared with basic SystemVerilog data types such as bit, logic,
byte, shortint, int, and
longint. |
| Typed localparam declaration | Yes | Supports localparams declared with basic SystemVerilog data types such as bit, logic,
byte, shortint, int, and
longint. |
| const declaration | No |
Others Constructs
| SystemVerilog Constructs | Supported? | Comments |
|---|---|---|
const | No | – |
unsigned | Yes | – |
| .name (implicit port connection) | No | – |
| .* (wildcard port connection) | No | – |
| Case equality operators (===, !==) | No | – |
Limitations
The following types of constructs are not supported and result in errors:
Classes and object-oriented programming (OOP) features
Assertions and coverage constructs
Dynamic arrays, associative arrays, and queues
Randomization and constraint-related constructs
Direct Programming Interface (DPI) constructs
Testbench-only constructs
