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Supported Verilog Constructs for HDL Import

Use importhdl function to import synthesizable Verilog® code into the Simulink® modeling environment. Make sure that the constructs used in the HDL code are supported by HDL import.

These tables list the supported Verilog constructs that you can use when you import your HDL code. If you use an unsupported construct, HDL import generates an error when parsing the input HDL file. Verilog HDL import can sometimes ignore the presence of certain constructs in the HDL code. To learn more, see the Comments section of the table.

Module Definition and Instantiations

Verilog ConstructsSupported?Comments
Library declarationNo–
Configuration declarationNo–
Module declarationYesMultiple sample rates and multiple clock inputs are not supported.
Module parameter port listYes–
Port declarationsYesINOUT ports are not supported.
Module without portsNo–
Local parameter declarationYes–
Parameter declarationYesYou can use parameters and constants that have a maximum size of 64 bits. By default, the parameter size is 32 bits.
Module instantiationYes

  • Unconnected ports in the instantiated modules are removed when importing the Verilog code.

  • Recursive module instantiation is not supported.

    Instead, if your top module instantiates modules that are defined in recursive subfolders, importhdl parses all Verilog files. For example, in this figure, importhdl can parse both DFF_Instantiation.v and TFF_Instantiation.v that are instantiated in DFF.v.

    Folder structure containing subfolders.

Data Types and Vectors

Verilog ConstructsSupported?Comments
Net declaration (Wire, Supply0, Supply1)Yes–
Real declarationNo–
String declarationNo–
Vector declarationYes–
Array support and array indexingYes–
Reg declarationYes–
Integer declarationYes–

Identifiers and Comments

Verilog ConstructsSupported?Comments
Lexical tokens (Whitespace, operator, comment)Yes–
Identifiers (Simple, Escaped)Yes–
System Functions ($signed, $unsigned)Yes–
Attribute instancesNoHDL import ignores these constructs.
CommentsNoHDL import ignores these constructs.
Numbers (Decimal, Binary, Hexadecimal, and Octal)Yes–
Compiler directives (`define,`undef, `ifndef, `else if)Yes–

Assignments

Verilog ConstructsSupported?Comments
Continuous assignmentYes–
Blocking assignmentYes--
Nonblocking assignmentYes–
Procedural assignment (Always block)Yes–

Operators

Verilog ConstructsSupported?Comments
Arithmetic operators (+, -, *, **, /, <<<, >>>)Yes–
Logical operators (<<, >>, !, &&, | |, ==, !=)Yes–
Relational operators (>, <, >=, <=, ==, !=) Yes–
Bitwise operators (~, &, |, ^, ~^, ^~)Yes–
Unary operators (+, -)YesSupported for restricted data types
Power operatorsYesSupported for restricted data types
Conditional operators (?:)Yes–
ConcatenationYes–
Bit SelectYes–
Reduction operators (&, ~&, |, ~|, ^, ~^, or ^~)Yes–

For an example that illustrates how to use different operators, see Generate Simulink Model from Verilog Code for Various Operators.

Conditional and Looping Statements

Verilog ConstructsSupported?Comments
If-else statementYes–
Conditional operators (?:)Yes–
For loopYes–
Loop Generate constructYesSupports loop generate constructs such as for-generate, case-generate, and if-generate constructs.
Conditional Generate constructNo–
Generate regionNo–
Genvar declarationNo–
Case statementYescasex and casez statements are also supported.

Procedural Blocks and Events

Verilog ConstructsSupported?Comments
Task declarationNo–
Initial construct (ROM modeling)No–
Sequential blocksYes–
Block declarationsYes–
Event control statementsYes–
Function callsYesHDL import does not support recursive function calls.
Task enableNo–
Always constructYes–
Function declarationYes–

Other Constructs

Verilog ConstructsSupported?Comments
Gate instantiationNo–
SpecparamsNo–
Specify blockNo–
Semantic verification (unused ports, correct module instantiation)Yes–
Clock bundle identificationYesMultiple sample rates and multiple clock signals are not supported.
Register inferenceYes–
Compare to Constant block inferenceYes–
Gain block inferenceYes–
RAM inferenceYes–
ROM inferenceNo–
Counter inferenceNo–
Drive strengthNo–

Limitations and Considerations

Verilog import does not support:

  • Importing of Verilog files from a read-only folder.

  • Generation of the preprocessing files in a read-only file system that parses the HDL code you input to the importhdl function.

  • Attribute instances and comments, which are ignored.

  • (#)delay values, such as #25, which are ignored.

  • Enumeration data types.

  • More than one clock signal.

  • Modules that are multirate.

  • Recursive module instantiation.

  • Multiport Switch inference with more than 1024 inputs. If you specify more than 1024 inputs to a Multiport Switch block that gets inferred from the Verilog code, Verilog import generates an error. The error is generated because the Simulink modeling environment does not support more than 1024 inputs for the block.

  • ROM detection from the Verilog code.

  • Importing of HDL files that use unsupported dataflow modeling patterns. See Unsupported Verilog Dataflow Patterns.

See Also

Functions

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