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Supported VHDL Constructs When Generating Simulink Models from VHDL Code

You can use importhdl function to generate a Simulink® model from synthesizable VHDL® code. To import VHDL code, you must use constructs that the importhdl function supports.

Supported VHDL Constructs

These tables list the supported VHDL constructs. If you use an unsupported construct, the function generates an error when parsing the input VHDL file. The importhdl can sometimes ignore the presence of certain constructs in the VHDL code. To learn more, see the Comments column of the table.

Entity and Architecture Declaration

VHDL ConstructsSupported?Comments
Entity declarationYes–
Architecture declarationYesDoes not support multiple architectures for single entities.
Port declarationYesDoes not support arrays of ports.
Signal declarationYes–
Generic clauseYes–

Package and Library Declaration

VHDL ConstructsSupported?Comments
Package declarationYesSupports only type declarations and constants.
Type declarationYesSupports only enumerations, integers, and arrays.
Package BodyNo–
Subtype declarationNo–
Constant declarationYes–
Variable declarationYes–
Use clauseYes–
Library declarationYesSupports only IEEE® and work library declarations.

Component and Configuration Declaration

VHDL ConstructsSupported?Comments
Configuration declarationNo–
Configuration specificationYesIgnored
Component declarationYesIgnored
Component instantiationYes–

Data Types and Vectors

VHDL ConstructsSupported?Comments
Integer declarationYes–
Real declarationNo–
String declarationNo–
Bit_vectorYes–
EnumeratedYes

Supports only 0 and 1 among character literals.

Does not support arrays of enumerated types.

Std_logicYesDoes not support values other than 0 and 1, such as U, X, Z, W, L, H.
Vector declarationYes–

Identifiers and Comments

VHDL ConstructsSupported?Comments
Numbers (based, normal)YesDoes not support real numbers that have decimal points.
IdentifiersYesDoes not support extended identifiers.
Standard package functionsYesSupports only resize, to_std_logic_vector, to_integer, to_signed, and to_unsigned.
Attribute specificationNo–
Attribute declarationNo–
RecordsNo–
Comments(Block and Single line)Yes–

Assignments

VHDL ConstructsSupported?Comments
Assignment statements (signal, variable)Yes–
Selected signal assignmentNo–

Operators

VHDL ConstructsSupported?Comments
Arithmetic operators (+,-,*, mod)YesDoes not support the remainder (rem) operator.
Relational operators (<, >, <<. >>)Yes–
Unary operators (+,-)Yes–
Logical operators (and, or, xor, nand, and nor)Yes–
Absolute and exponential operators (abs, **) Yes–
Shift operators (sll, srl, sla, sra, rol, and ror)Yes–

Conditional and Looping Statements

VHDL ConstructsSupported?Comments
If-else statementYes–
Case statementYes–
Condition operators (??)No–
Assertion statementsNo–
For loopYesParameter specifications that use a discrete subtype, such as enumerations, are not supported.
Loop statementsNo–
Generate statementNoSupports only the for generate statement.

Process Statements and Procedure Definitions

VHDL ConstructsSupported?Comments
Process statementYes–
FunctionsNo–
BlocksNo–
Procedure definitionsNo–
Function callsNo–

Event Control Statements

VHDL ConstructsSupported?Comments
Waveform conditionYesTime expressions are not supported.
Wait statementYesOnly supports wait statements that only use the until clause.
Exit statementNo–
Null statementNo–
Return statementNo–

Limitations and Considerations

VHDL import does not support:

  • Importing of VHDL files from a read-only folder.

  • Generation of the preprocessing files in a read-only file system that parses the HDL code you input to the importhdl function.

  • Element associations with range choice and mixed choices.

  • Multiple architectures associated with single entity.

  • More than one clock signal.

  • Modules that are multirate.

  • Recursive entity instantiation.

  • Multiport Switch inference with more than 1024 inputs. If you specify more than 1024 inputs in function in the VHDL code that the importhdl function imports as a Multiport Switch block, the VHDL import generates an error. The Simulink modeling environment does not support more than 1024 inputs for the block.

  • ROM detection from the VHDL code.

See Also

Functions

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