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hdlverifier.FILFreeRunning

Free-running FIL simulation with MATLAB

Since R2024b

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Description

Connect an FPGA-in-the-loop simulation to a MATLAB® testbench in free-running clock mode.

The FILFreeRunning object connects the FPGA simulation to a MATLAB testbench in free-running clock mode. Use the writePort and readPort methods to send and receive sample or frame data to or from the FPGA device under test (DUT). For more information, see What Is Free-Running FPGA-in-the-Loop?

To run a simulation consisting of a MATLAB testbench communicating with an FPGA simulation:

  1. Customize the hdlverifier.FILFreeRunning object using FPGA-in-the-Loop Wizard.

  2. Create the object in your design and set its properties.

  3. Call the object with arguments, as if it were a function.

Creation

To create an hdlverifier.FILFreeRunning object, use the FPGA-in-the-Loop Wizard to customize the FILFreeRunning object. The output of the FIL wizard is a file called toplevel_fil, where toplevel is the name of the top level HDL module. You can then create the object by assigning it to a local variable.

filobj = toplevel_fil creates the object customized by the FPGA-in-the-Loop Wizard.

You can adjust writable properties after creating the object:

filobj = toplevel_fil;
filObj.StreamingOutputSigned = {false};

Properties

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This property is read-only.

Design under test (DUT) top-level name, specified as a character vector or string scalar.

Example: 'inverter_top'

This property is read-only.

Names of DUT input ports that support streaming data, specified as a cell array of character vectors. Use the writePort object function to send streaming data to these ports.

This property is read-only.

Data widths in bits of streaming input ports, specified as a cell array of integers.

Example: {12,6,1} – The design has three inputs: One is 12 bits wide, one is 6 bits wide, and one is 1 bit wide.

This property is read-only.

Names of DUT input ports that support streaming data, specified as a cell array of character vectors. Use the readPort object function to receive streaming data from these ports.

This property is read-only.

Data widths in bits of streaming output ports, specified as a cell array of integers.

Example: {12,6,1} – The design has three outputs: one is 12 bits wide, one is 6 bits wide, and one is 1 bit wide.

Output data types, specified as a cell array of the following types:

  • 'logical'

  • 'integer'

  • 'half'

  • 'single'

  • 'double'

  • 'fixedpoint'

Example: {'integer','fixedpoint','integer'}

Output fraction lengths, specified as a cell array of integers.

Example: {16,8} — One output fraction length is 16 bits and the other has a fraction length of 8 bits.

Sign of the outputs, specified as a cell array of false (unsigned) or true (signed).

Example: {true, true, false} — Three outputs consist of a signed value, an unsigned value, and a signed value.

This property is read-only.

Control input port names in the HDL top-level module, specified as cell array of character vectors.

Example: {'in1','in2'}

This property is read-only.

Control input widths in bits, specified as a cell array of integers. When this property is an integer, all inputs have the same bit width.

Example: {12,6,1} – The design has three control inputs: One is 12 bits wide, one is 6 bits wide, and one is 1 bit wide.

This property is read-only.

Control output port names in the HDL top-level module, specified as a cell array of character vectors, string scalar, or string array.

Example: {'out1','out2'}

This property is read-only.

Control output widths in bits, specified as a cell array of integers.

Example: {12,6,1} – The design has three control outputs: One is 12 bits wide, one is 6 bits wide, and one is 1 bit wide.

Control output data types, specified as a cell array of the following types:

  • 'logical'

  • 'integer'

  • 'half'

  • 'single'

  • 'fixedpoint'

Example: {'integer','fixedpoint','integer'}

Control output fraction lengths, specified as a cell array of integers.

Example: {16,8} — One output fraction length is 16 bits, and the other one has a fraction length of 8 bits.

Sign of control outputs, specified as a cell array of false (unsigned), or true (signed).

Example: {true, true, false} — Three outputs consisting of a signed value, an unsigned value, and a signed value.

Hardware overclocking factor, specified as an integer.

Example: 3

Frame length of streaming output, specified as an integer.

Example: 2048

Timeout for streaming input and output ports, in seconds, specified as an integer.

This property is read-only.

Parameters for the connection with the FPGA board, specified as a character vector or string scalar. The vector consists of three parts:

This property is read-only.

Name of the FPGA chip vendor, specified as 'Xilinx' or 'Altera'.

Example: 'Xilinx'

This property is read-only.

FPGA board name, specified as a character vector or string scalar.

This property is read-only.

Selected between Vivado® or Quartus®.

Path to the FPGA programming file, specified as a character vector or string scalar.

Example: 'c:\work\filename'

This property is read-only.

Position of the FPGA in the JTAG scan chain, specified as a positive integer.

Example: 1

This property is read-only.

Path to device tree file, specified as a character vector or string scalar.

Internet Protocol Address for the board.

Example: '192.168.0.2'

Username for the board, specified as a character vector or string scalar.

Password for the board, specified as a character vector or string scalar.

Specify Ethernet interface type.

Object Functions

writePortSend data to DUT ports
readPortReceive data from DUT ports
programFPGA Load programming file associated with FILSimulation or FILFreeRunning system object onto FPGA
releaseRelease resources and allow changes to System object property values and input characteristics

Version History

Introduced in R2024b

See Also

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