hdlverifier.FILSimulation
FIL simulation with MATLAB
Description
The FILSimulation
System object™ connects an FPGA execution to a MATLAB® testbench. It does so by applying input signals to and reading output signals
from an HDL model running on an FPGA. You can use this object to model a source or sink device
by configuring the object with input or output ports only.
To run a simulation consisting of a MATLAB testbench communicating with an FPGA execution:
Customize the hdlverifier.FILSimulation object using FPGA-in-the-Loop Wizard.
Create the object in your design and set its properties.
Call the object with arguments, as if it were a function.
To learn more about how System objects work, see What Are System Objects?.
Creation
To create an hdlverifier.FILSimulation
System object, use the FPGA-in-the-Loop Wizard to customize the FILSimulation
System object. The output of the FILWizard is a file called
toplevel
_fil, where toplevel
is the
name of the top level HDL module. You can then create the System object by assigning it to a
local variable.
filobj = toplevel_fil
creates the System object customized by the
FPGA-in-the-Loop Wizard. toplevel
is the name of the top-level module in
your HDL code.
You can create the System object and set its properties:
filobj = toplevel_fil('InputSignals', {'/top/in1','/top/in2'}, ... 'OutputSignals', {'/top/out1','/top/out2'}, ... 'OutputDataTypes', {'double','fixedpoint'}, ... 'OutputSigned', [true,false]);
filobj = toplevel_fil; filobj.OutputDataTypes = char('fixedpoint', 'integer', 'fixedpoint'); filObj.OutputSigned = [false, true, true];
Properties
Usage
Description
[
connects to the FPGA, writes hdloutputs
] = filobj([hdlinputs
])hdlinputs
to the FPGA and reads
hdloutputs
from the FPGA.
Input Arguments
Output Arguments
Object Functions
To use an object function, specify the
System object as the first input argument. For
example, to release system resources of a System object named obj
, use
this syntax:
release(obj)
Examples
Version History
Introduced in R2012b