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Generate Parameterized UVM Testbench from Simulink
This example shows how to develop a design and testbench in Simulink® and generate an equivalent simulation for a universal verification methodology (UVM) environment using uvmbuild. You can then extend this testbench to refine your verification using protocol-specific drivers, constrained random sequences, and parameterized scoreboards.
Introduction
This example walks you through a top-down design development process of an HDL implementation. In such a workflow, you design a behavioral algorithm in Simulink and test it using surrounding blocks for stimulus generation and results checking. Once the simulation confirms that the design meets its requirements, you deliver any collateral needed to the downstream HDL implementation team. You need to reverify that the HDL implementation meets the requirements as simulated in Simulink as well as any other unique aspects of the design, such as protocol interfaces that were not modeled in Simulink.
Ordinarily, the hand-off process can be tedious and the source of many errors. The HDL implementation and HDL design verification (DV) engineers must:
Translate written specifications to HDL and testing environments.
Understand the run-time behavior of the Simulink simulation environment such as how the stimulus is created, processed, and checked.
Translate the run-time behaviors to SystemVerilog implementations.
Integrate the stimulus, design, and response checking into a runnable SystemVerilog model to confirm that the translated behaviors behave the same as the original Simulink simulation.
Integrate these main SystemVerilog components into a UVM context to allow extending the Simulink testing with DV-authored verification. This extended testing might include randomized testing, SystemVerilog assertions, functional coverage, and code coverage.
The HDL Verifier™ UVM generation capabilities automate this hand-off process. The DV engineer gets a verified UVM test environment that matches the testing performed in Simulink and can easily update that environment to meet their downstream verification needs.
Design and Test in Simulink
Write your algorithm and add a testbench to it. The model consists of typical subsystems for a testbench such as stimulus generation, the design under test (DUT), and response checking.
In this design, the source subsystem creates a random pulse of 64 samples of information embedded at a random location in a 5000-sample frame of noise. It also generates a set of 64 optimal matched filter coefficients for detection of the pulse. The inputs are fed to both the design and the response checker. The response checker verifies that the pulse is detected at the right location in the noisy waveform. Proper operation is confirmed through console output. If the expected power of the detected signal is not within certain limits, an assertion is fired.
openProject('pulsedetector_proj'); model = 'pulsedetector_tb'; open_system(model);
Simulating the model provides confirmation that, in five generated pulses, five are detected. A three paneled figure shows a Tx Signal (the original pulse), an Rx Signal (the pulse embedded in noise), and the filtered output of a reference implementation that shows where a peak is detected. The output signal is delayed by one frame.
sim(model);
[FrameNum= 0] No peak found in Ref or Impl. [FrameNum= 1] PREDICTED: Peak location=2163.000000, mag-squared=0.280 using global max [FrameNum= 1] ACTUAL : Peak location=2170.000000, mag-squared=0.285 using global max [FrameNum= 1] DIFF : Peak location=7, mag-squared=0.004 (1.551%) [FrameNum= 2] PREDICTED: Peak location=2163.000000, mag-squared=0.200 using global max [FrameNum= 2] ACTUAL : Peak location=2170.000000, mag-squared=0.194 using global max [FrameNum= 2] DIFF : Peak location=7, mag-squared=0.006 (2.881%) [FrameNum= 3] PREDICTED: Peak location=2163.000000, mag-squared=0.224 using global max [FrameNum= 3] ACTUAL : Peak location=2170.000000, mag-squared=0.234 using global max [FrameNum= 3] DIFF : Peak location=7, mag-squared=0.010 (4.623%) [FrameNum= 4] PREDICTED: Peak location=2163.000000, mag-squared=0.200 using global max [FrameNum= 4] ACTUAL : Peak location=2170.000000, mag-squared=0.209 using global max [FrameNum= 4] DIFF : Peak location=7, mag-squared=0.009 (4.346%) [FrameNum= 5] PREDICTED: Peak location=2163.000000, mag-squared=0.255 using global max [FrameNum= 5] ACTUAL : Peak location=2170.000000, mag-squared=0.257 using global max [FrameNum= 5] DIFF : Peak location=7, mag-squared=0.002 (0.735%) [FrameNum= 6] PREDICTED: Peak location=2163.000000, mag-squared=0.241 using global max [FrameNum= 6] ACTUAL : Peak location=2170.000000, mag-squared=0.250 using global max [FrameNum= 6] DIFF : Peak location=7, mag-squared=0.009 (3.660%) [FrameNum= 7] PREDICTED: Peak location=2163.000000, mag-squared=0.241 using global max [FrameNum= 7] ACTUAL : Peak location=2170.000000, mag-squared=0.243 using global max [FrameNum= 7] DIFF : Peak location=7, mag-squared=0.002 (0.790%) [FrameNum= 8] PREDICTED: Peak location=2163.000000, mag-squared=0.225 using global max [FrameNum= 8] ACTUAL : Peak location=2170.000000, mag-squared=0.231 using global max [FrameNum= 8] DIFF : Peak location=7, mag-squared=0.007 (3.076%) [FrameNum= 9] PREDICTED: Peak location=2163.000000, mag-squared=0.239 using global max [FrameNum= 9] ACTUAL : Peak location=2170.000000, mag-squared=0.254 using global max [FrameNum= 9] DIFF : Peak location=7, mag-squared=0.015 (6.083%)
Warning: Assertion detected in '<a href="matlab:open_and_hilite_hyperlink ('pulsedetector_tb/CheckDetection/Check Static Upper Bound','error')">pulsedetector_tb/CheckDetection/Check Static Upper Bound</a>' at time 9
[FrameNum= 10] PREDICTED: Peak location=2163.000000, mag-squared=0.225 using global max [FrameNum= 10] ACTUAL : Peak location=2170.000000, mag-squared=0.230 using global max [FrameNum= 10] DIFF : Peak location=7, mag-squared=0.005 (2.242%)
Generate an Executable UVM Testbench
Use the uvmbuild function to export your design to a UVM environment. The UVM testbench provides structure to the HDL verification process and allows for all of the Simulink testbench components and test cases to be reused by the implementation verification team. Standard component definitions separate the pieces of the environment by their role in the simulation. For this example:
PulseDetectorsubsystem is mapped to the DUT SystemVerilog module.GenPulsesubsystem is mapped to thesequence_itemcreation for the Sequencer UVM component.CheckDetectionsubsystem is mapped to the Scoreboard UVM component.PulseDetectorRefsubsystem is mapped to the Predictor UVM component.
Run these commands to build the design.
% Generate a UVM testbench design = [model '/PulseDetector']; sequence = [model '/GenPulse']; scoreboard = [model '/CheckDetection']; predictor = [model '/PulseDetectorRef']; driver = [model '/InputDriver']; monitor = [model '/OutputMonitor']; uvmbuild(design, sequence, scoreboard, Predictor=predictor, Driver=driver, Monitor=monitor)
### Starting DPI subsystem generation for UVM test bench ### Starting build procedure for model: PulseDetector ### Starting SystemVerilog DPI Component Generation ### Generating DPI H Wrapper PulseDetector_dpi.h ### Generating DPI C Wrapper PulseDetector_dpi.c ### Generating UVM module package PulseDetector_dpi_pkg.sv ### Generating SystemVerilog module PulseDetector_dpi.sv ### Generating makefiles for: PulseDetector_dpi ### Invoking make to build the DPI Shared Library ### Successful completion of build procedure for model: PulseDetector Build Summary Top model targets: Model Build Reason Status Build Duration ================================================================================================================ PulseDetector Information cache folder or artifacts were missing. Code generated and compiled. 0h 0m 9.1956s 1 of 1 models built (0 models already up to date) Build duration: 0h 0m 9.7003s ### Starting build procedure for model: GenPulse ### Starting SystemVerilog DPI Component Generation ### Generating DPI H Wrapper GenPulse_dpi.h ### Generating DPI C Wrapper GenPulse_dpi.c ### Generating UVM module package GenPulse_dpi_pkg.sv ### Generating SystemVerilog module GenPulse_dpi.sv ### Generating makefiles for: GenPulse_dpi ### Invoking make to build the DPI Shared Library ### Successful completion of build procedure for model: GenPulse Build Summary Top model targets: Model Build Reason Status Build Duration =========================================================================================================== GenPulse Information cache folder or artifacts were missing. Code generated and compiled. 0h 0m 11.023s 1 of 1 models built (0 models already up to date) Build duration: 0h 0m 11.361s ### Starting build procedure for model: InputDriver ### Starting SystemVerilog DPI Component Generation ### Generating DPI H Wrapper InputDriver_dpi.h ### Generating DPI C Wrapper InputDriver_dpi.c ### Generating UVM module package InputDriver_dpi_pkg.sv ### Generating SystemVerilog module InputDriver_dpi.sv ### Generating makefiles for: InputDriver_dpi ### Invoking make to build the DPI Shared Library ### Successful completion of build procedure for model: InputDriver Build Summary Top model targets: Model Build Reason Status Build Duration ============================================================================================================== InputDriver Information cache folder or artifacts were missing. Code generated and compiled. 0h 0m 6.6374s 1 of 1 models built (0 models already up to date) Build duration: 0h 0m 6.9772s ### Starting build procedure for model: OutputMonitor ### Starting SystemVerilog DPI Component Generation ### Generating DPI H Wrapper OutputMonitor_dpi.h ### Generating DPI C Wrapper OutputMonitor_dpi.c ### Generating UVM module package OutputMonitor_dpi_pkg.sv ### Generating SystemVerilog module OutputMonitor_dpi.sv ### Generating makefiles for: OutputMonitor_dpi ### Invoking make to build the DPI Shared Library ### Successful completion of build procedure for model: OutputMonitor Build Summary Top model targets: Model Build Reason Status Build Duration ================================================================================================================ OutputMonitor Information cache folder or artifacts were missing. Code generated and compiled. 0h 0m 6.4048s 1 of 1 models built (0 models already up to date) Build duration: 0h 0m 6.7688s ### Starting build procedure for model: CheckDetection ### Starting SystemVerilog DPI Component Generation ### Generating DPI H Wrapper CheckDetection_dpi.h ### Generating DPI C Wrapper CheckDetection_dpi.c ### Generating UVM module package CheckDetection_dpi_pkg.sv ### Generating SystemVerilog module CheckDetection_dpi.sv ### Generating makefiles for: CheckDetection_dpi ### Invoking make to build the DPI Shared Library ### Successful completion of build procedure for model: CheckDetection Build Summary Top model targets: Model Build Reason Status Build Duration ================================================================================================================= CheckDetection Information cache folder or artifacts were missing. Code generated and compiled. 0h 0m 11.548s 1 of 1 models built (0 models already up to date) Build duration: 0h 0m 11.93s ### Starting build procedure for model: PulseDetectorRef ### Starting SystemVerilog DPI Component Generation ### Generating DPI H Wrapper PulseDetectorRef_dpi.h ### Generating DPI C Wrapper PulseDetectorRef_dpi.c ### Generating UVM module package PulseDetectorRef_dpi_pkg.sv ### Generating SystemVerilog module PulseDetectorRef_dpi.sv ### Generating makefiles for: PulseDetectorRef_dpi ### Invoking make to build the DPI Shared Library ### Successful completion of build procedure for model: PulseDetectorRef Build Summary Top model targets: Model Build Reason Status Build Duration =================================================================================================================== PulseDetectorRef Information cache folder or artifacts were missing. Code generated and compiled. 0h 0m 8.6281s 1 of 1 models built (0 models already up to date) Build duration: 0h 0m 8.9672s ### Starting UVM test bench generation for model: pulsedetector_tb ### Generating UVM transaction object ./uvm_build/pulsedetector_tb_uvm_testbench/scoreboard/mw_PulseDetector_scoreboard_trans.sv ### Generating UVM interface ./uvm_build/pulsedetector_tb_uvm_testbench/uvm_artifacts/mw_PulseDetector_if.sv ### Generating UVM sequence ./uvm_build/pulsedetector_tb_uvm_testbench/sequence/mw_PulseDetector_sequence.sv ### Generating UVM sequencer ./uvm_build/pulsedetector_tb_uvm_testbench/sequence/mw_PulseDetector_sequencer.sv ### Generating UVM sequence transaction ./uvm_build/pulsedetector_tb_uvm_testbench/sequence/mw_PulseDetector_sequence_trans.sv ### Generating UVM driver ./uvm_build/pulsedetector_tb_uvm_testbench/driver/mw_PulseDetector_driver.sv ### Generating UVM monitor ./uvm_build/pulsedetector_tb_uvm_testbench/monitor/mw_PulseDetector_monitor.sv ### Generating UVM input monitor ./uvm_build/pulsedetector_tb_uvm_testbench/uvm_artifacts/mw_PulseDetector_monitor_input.sv ### Generating UVM Reference Model ./uvm_build/pulsedetector_tb_uvm_testbench/predictor/mw_PulseDetector_predictor.sv ### Generating UVM transaction object ./uvm_build/pulsedetector_tb_uvm_testbench/predictor/mw_PulseDetector_predictor_trans.sv ### Generating UVM agent ./uvm_build/pulsedetector_tb_uvm_testbench/uvm_artifacts/mw_PulseDetector_agent.sv ### Generating UVM scoreboard ./uvm_build/pulsedetector_tb_uvm_testbench/scoreboard/mw_PulseDetector_scoreboard.sv ### Generating UVM scoreboard configuration object ./uvm_build/pulsedetector_tb_uvm_testbench/scoreboard/mw_PulseDetector_scoreboard_cfg_obj.sv ### Generating UVM environment ./uvm_build/pulsedetector_tb_uvm_testbench/uvm_artifacts/mw_PulseDetector_environment.sv ### Generating UVM test ./uvm_build/pulsedetector_tb_uvm_testbench/uvm_artifacts/mw_PulseDetector_test.sv ### Generating UVM top ./uvm_build/pulsedetector_tb_uvm_testbench/top/mw_PulseDetector_top.sv ### Generating UVM test package ./uvm_build/pulsedetector_tb_uvm_testbench/top/pulsedetector_tb_pkg.sv ### Generating UVM test bench simulation script for Siemens Questa/ModelSim ./uvm_build/pulsedetector_tb_uvm_testbench/top/run_tb_mq.do
The architecture of the generated UVM testbench is shown below. The DUT for this model is PulseDetector.
Each of the highlighted pieces of the UVM testbench are implemented by wrapping generated C-code from the Simulink subsystem and calling its entry points using DPI. The following image shows a couple of the function declarations for the PulseDetector subsystem.
The SystemVerilog UVM code determines the timing of the DPI calls. For example, in the PulseDetector SystemVerilog module:
The "initialize" DPI call is triggered by an "initial" code block.
The "terminate" DPI call is triggered by a "final" code block.
The "output" and "update" DPI calls are triggered by a rising clock edge where the clock enable is active.
Run the UVM Testbench
The uvmbuild process also generates a script to run a simulation of the UVM test. Scripts are generated for the following simulators:
Siemens® ModelSim™ and Questa™: run_tb_mq.do
Cadence® Xcelium™: run_tb_xcelium.sh
Synopsys® VCS®: run_tb_vcs.sh
The generated script for ModelSim is shown.
Execute the generated script to verify the UVM execution matches the Simulink execution. Because the sequence is parameterized with the SNR input port, its default value is 0.0 in UVM. To properly compare the simulation runs, change its default value to 2.0 (which has a bit value of 0b10_000000), to match Simulink; this can be done via a plusarg which we pass to the script via an environment variable.
First, set up the necessary environment to run Questa. The provided script is MathWorks-specific. Adjust the commands to match your installation, or choose to use a different simulator.
setup_questa();
Next, set up variables that affect the HDL simulation scripts and then execute the UVM simulation. Notice how the simulation log shows the same diagnostic messages as we saw in Simulink.
% Clear environment variables that influence the UVM simulation' setenv EXTRA_UVM_SIM_ARGS setenv EXTRA_UVM_COMP_ARGS setenv UVM_TOP_MODULE % Choose a simulator current_simulator = 'Questa'; % Simulate the UVM testbench using an SNR of 2.0 cd uvm_build/pulsedetector_tb_uvm_testbench/top setenv EXTRA_UVM_SIM_ARGS +SNR_default_inp_val=10000000 switch current_simulator case 'Questa', ! vsim -c -do run_tb_mq.do case 'Questa_gui', ! vsim -do run_tb_mq.do case 'Xcelium', ! ./run_tb_xcelium.sh case 'VCS', ! ./run_tb_vcs.sh end
Reading pref.tcl
# 2022.2
# do run_tb_mq.do
# +SNR_default_inp_val=10000000
# mw_PulseDetector_top.sv
# QuestaSim-64 vlog 2022.2 Compiler 2022.04 Apr 25 2022
# Start time: 14:22:06 on Jul 17,2024
# vlog -timescale 1ns/1ns ../DPI_dut/PulseDetector_dpi_pkg.sv ../sequence/GenPulse_dpi_pkg.sv ../scoreboard/CheckDetection_dpi_pkg.sv ../driver/InputDriver_dpi_pkg.sv ../monitor/OutputMonitor_dpi_pkg.sv ../predictor/PulseDetectorRef_dpi_pkg.sv pulsedetector_tb_pkg.sv mw_PulseDetector_top.sv "+define+MG_SIM"
# -- Compiling package PulseDetector_dpi_pkg
# -- Compiling package GenPulse_dpi_pkg
# -- Compiling package CheckDetection_dpi_pkg
# -- Compiling package InputDriver_dpi_pkg
# -- Compiling package OutputMonitor_dpi_pkg
# -- Compiling package PulseDetectorRef_dpi_pkg
# ** Note: (vlog-2286) pulsedetector_tb_pkg.sv(5): Using implicit +incdir+D:/3rdparty/R2023a/8709182/share/Questasim/Win/uvm-1.1d/../verilog_src/uvm-1.1d/src from import uvm_pkg
# -- Compiling package pulsedetector_tb_pkg
# -- Importing package mtiUvm.uvm_pkg (uvm-1.1d Built-in)
# -- Importing package GenPulse_dpi_pkg
# -- Importing package CheckDetection_dpi_pkg
# -- Importing package PulseDetectorRef_dpi_pkg
# -- Importing package InputDriver_dpi_pkg
# -- Importing package OutputMonitor_dpi_pkg
# ** Warning: ** while parsing file included at mw_PulseDetector_top.sv(5)
# ** at ../DPI_dut/PulseDetector_dpi.sv(15): (vlog-13314) Defaulting port 'coeff_in' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# -- Compiling package mw_PulseDetector_top_sv_unit
# -- Importing package PulseDetector_dpi_pkg
# -- Importing package pulsedetector_tb_pkg
# -- Compiling module PulseDetector_dpi
# ** Warning: ../DPI_dut/PulseDetector_dpi.sv(15): (vlog-13314) Defaulting port 'coeff_in' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# -- Compiling interface mw_PulseDetector_if
# -- Compiling module mw_PulseDetector_top
#
# Top level modules:
# mw_PulseDetector_top
# End time: 14:22:08 on Jul 17,2024, Elapsed time: 0:00:02
# Errors: 0, Warnings: 2
# vsim "+SNR_default_inp_val=10000000" -L work -voptargs="+acc" -sv_lib ../DPI_dut/PulseDetector_win64 -sv_lib ../sequence/GenPulse_win64 -sv_lib ../scoreboard/CheckDetection_win64 -sv_lib ../driver/InputDriver_win64 -sv_lib ../monitor/OutputMonitor_win64 -sv_lib ../predictor/PulseDetectorRef_win64 "+UVM_TESTNAME=mw_PulseDetector_test" mw_PulseDetector_top "+define+MG_SIM"
# Start time: 14:22:08 on Jul 17,2024
# ** Note: (vsim-3812) Design is being optimized...
# ** Warning: (vopt-10587) Some optimizations are turned off because the +acc switch is in effect. This will cause your simulation to run slowly. Please use -access/-debug to maintain needed visibility.
# ** Warning: ../DPI_dut/PulseDetector_dpi.sv(15): (vopt-13314) Defaulting port 'coeff_in' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Note: (vsim-12126) Error and warning message counts have been restored: Errors=0, Warnings=2.
# // Questa Sim-64
# // Version 2022.2 win64 Apr 25 2022
# //
# // Copyright 1991-2022 Mentor Graphics Corporation
# // All Rights Reserved.
# //
# // QuestaSim and its associated documentation contain trade
# // secrets and commercial or financial information that are the property of
# // Mentor Graphics Corporation and are privileged, confidential,
# // and exempt from disclosure under the Freedom of Information Act,
# // 5 U.S.C. Section 552. Furthermore, this information
# // is prohibited from disclosure under the Trade Secrets Act,
# // 18 U.S.C. Section 1905.
# //
# Loading sv_std.std
# Loading work.mw_PulseDetector_if(fast)
# Loading work.OutputMonitor_dpi_pkg(fast)
# Loading work.InputDriver_dpi_pkg(fast)
# Loading work.PulseDetectorRef_dpi_pkg(fast)
# Loading work.CheckDetection_dpi_pkg(fast)
# Loading work.GenPulse_dpi_pkg(fast)
# Loading mtiUvm.uvm_pkg(fast)
# Loading work.pulsedetector_tb_pkg(fast)
# Loading work.PulseDetector_dpi_pkg(fast)
# Loading work.mw_PulseDetector_top_sv_unit(fast)
# Loading mtiUvm.questa_uvm_pkg(fast)
# Loading work.mw_PulseDetector_top(fast)
# Loading work.mw_PulseDetector_if(fast__2)
# Loading work.PulseDetector_dpi(fast)
# Loading .\../DPI_dut/PulseDetector_win64.dll
# Loading .\../sequence/GenPulse_win64.dll
# Loading .\../scoreboard/CheckDetection_win64.dll
# Loading .\../driver/InputDriver_win64.dll
# Loading .\../monitor/OutputMonitor_win64.dll
# Loading .\../predictor/PulseDetectorRef_win64.dll
# Loading D:/3rdparty/R2023a/8709182/share/Questasim/Win/uvm-1.1d\win64\uvm_dpi.dll
[FrameNum= 0] No peak found in Ref or Impl.
[FrameNum= 1] PREDICTED: Peak location=2163.000000, mag-squared=0.280 using global max
[FrameNum= 1] ACTUAL : Peak location=2170.000000, mag-squared=0.285 using global max
[FrameNum= 1] DIFF : Peak location=7, mag-squared=0.004 (1.551%)
[FrameNum= 2] PREDICTED: Peak location=2163.000000, mag-squared=0.200 using global max
[FrameNum= 2] ACTUAL : Peak location=2170.000000, mag-squared=0.194 using global max
[FrameNum= 2] DIFF : Peak location=7, mag-squared=0.006 (2.881%)
[FrameNum= 3] PREDICTED: Peak location=2163.000000, mag-squared=0.224 using global max
[FrameNum= 3] ACTUAL : Peak location=2170.000000, mag-squared=0.234 using global max
[FrameNum= 3] DIFF : Peak location=7, mag-squared=0.010 (4.623%)
[FrameNum= 4] PREDICTED: Peak location=2163.000000, mag-squared=0.200 using global max
[FrameNum= 4] ACTUAL : Peak location=2170.000000, mag-squared=0.209 using global max
[FrameNum= 4] DIFF : Peak location=7, mag-squared=0.009 (4.346%)
[FrameNum= 5] PREDICTED: Peak location=2163.000000, mag-squared=0.255 using global max
[FrameNum= 5] ACTUAL : Peak location=2170.000000, mag-squared=0.257 using global max
[FrameNum= 5] DIFF : Peak location=7, mag-squared=0.002 (0.735%)
[FrameNum= 6] PREDICTED: Peak location=2163.000000, mag-squared=0.241 using global max
[FrameNum= 6] ACTUAL : Peak location=2170.000000, mag-squared=0.250 using global max
[FrameNum= 6] DIFF : Peak location=7, mag-squared=0.009 (3.660%)
[FrameNum= 7] PREDICTED: Peak location=2163.000000, mag-squared=0.241 using global max
[FrameNum= 7] ACTUAL : Peak location=2170.000000, mag-squared=0.243 using global max
[FrameNum= 7] DIFF : Peak location=7, mag-squared=0.002 (0.790%)
[FrameNum= 8] PREDICTED: Peak location=2163.000000, mag-squared=0.225 using global max
[FrameNum= 8] ACTUAL : Peak location=2170.000000, mag-squared=0.231 using global max
[FrameNum= 8] DIFF : Peak location=7, mag-squared=0.007 (3.076%)
[FrameNum= 9] PREDICTED: Peak location=2163.000000, mag-squared=0.239 using global max
[FrameNum= 9] ACTUAL : Peak location=2170.000000, mag-squared=0.254 using global max
[FrameNum= 9] DIFF : Peak location=7, mag-squared=0.015 (6.083%)
[FrameNum= 10] PREDICTED: Peak location=2163.000000, mag-squared=0.225 using global max
[FrameNum= 10] ACTUAL : Peak location=2170.000000, mag-squared=0.230 using global max
[FrameNum= 10] DIFF : Peak location=7, mag-squared=0.005 (2.242%)
[FrameNum= 11] PREDICTED: Peak location=2163.000000, mag-squared=0.207 using global max
[FrameNum= 11] ACTUAL : Peak location=2170.000000, mag-squared=0.221 using global max
[FrameNum= 11] DIFF : Peak location=7, mag-squared=0.014 (6.697%)
[FrameNum= 12] PREDICTED: Peak location=2163.000000, mag-squared=0.265 using global max
[FrameNum= 12] ACTUAL : Peak location=2170.000000, mag-squared=0.260 using global max
[FrameNum= 12] DIFF : Peak location=7, mag-squared=0.005 (2.014%)
# ----------------------------------------------------------------
# UVM-1.1d
# (C) 2007-2013 Mentor Graphics Corporation
# (C) 2007-2013 Cadence Design Systems, Inc.
# (C) 2006-2013 Synopsys, Inc.
# (C) 2011-2013 Cypress Semiconductor Corp.
# ----------------------------------------------------------------
#
# *********** IMPORTANT RELEASE NOTES ************
#
# You are using a version of the UVM library that has been compiled
# with `UVM_NO_DEPRECATED undefined.
# See http://www.eda.org/svdb/view.php?id=3313 for more details.
#
# You are using a version of the UVM library that has been compiled
# with `UVM_OBJECT_MUST_HAVE_CONSTRUCTOR undefined.
# See http://www.eda.org/svdb/view.php?id=3770 for more details.
#
# (Specify +UVM_NO_RELNOTES to turn off this notice)
#
# UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(277) @ 0: reporter [Questa UVM] QUESTA_UVM-1.2.3
# UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(278) @ 0: reporter [Questa UVM] questa_uvm::init(+struct)
# UVM_INFO @ 0: reporter [RNTST] Running test mw_PulseDetector_test...
# ** Info: Gathering coverage for 2 Simulink verify() calls.
# Time: 0 ns Scope: CheckDetection_dpi_pkg.VerifyInterfaceT.initVerifyInfo File: ../scoreboard/CheckDetection_dpi_pkg.sv Line: 261
# ** Info: Model verify() covergroup 0 properties:
# Covergroup instance name: pulsedetector_tb:757
# Coverage count goal : 1
# Model location : Simulink.ID.hilite('pulsedetector_tb:757')
# Block path : CheckDetection/CheckDetection/Check
# Static Range
# Step name : inferred verify call
# Verify ID : CheckDetection/CheckDetection/Check
# Static Range
# Time: 0 ns Scope: CheckDetection_dpi_pkg.VerifyInterfaceT.initVerifyInfo File: ../scoreboard/CheckDetection_dpi_pkg.sv Line: 265
# ** Info: Model verify() covergroup 1 properties:
# Covergroup instance name: pulsedetector_tb:744
# Coverage count goal : 1
# Model location : Simulink.ID.hilite('pulsedetector_tb:744')
# Block path : CheckDetection/CheckDetection/Check Static
# Upper Bound
# Step name : inferred verify call
# Verify ID : CheckDetection/CheckDetection/Check Static
# Upper Bound
# Time: 0 ns Scope: CheckDetection_dpi_pkg.VerifyInterfaceT.initVerifyInfo File: ../scoreboard/CheckDetection_dpi_pkg.sv Line: 265
# ** Error: pulsedetector_tb:744:
# Time: 450020 ns Scope: pulsedetector_tb_pkg.mw_PulseDetector_scoreboard.run_phase File: ../scoreboard/mw_PulseDetector_scoreboard.sv Line: 84
# ** Error: pulsedetector_tb:744: At step 'inferred verify call' verify id 'CheckDetection/CheckDetection/Check Static
# Upper Bound' Failed
# Time: 450020 ns Scope: CheckDetection_dpi_pkg.VerifyInterfaceT.checkVerifyStatus File: ../scoreboard/CheckDetection_dpi_pkg.sv Line: 384
# ** Error: pulsedetector_tb:744:
# Time: 550020 ns Scope: pulsedetector_tb_pkg.mw_PulseDetector_scoreboard.run_phase File: ../scoreboard/mw_PulseDetector_scoreboard.sv Line: 84
# ** Error: pulsedetector_tb:744: At step 'inferred verify call' verify id 'CheckDetection/CheckDetection/Check Static
# Upper Bound' Failed
# Time: 550020 ns Scope: CheckDetection_dpi_pkg.VerifyInterfaceT.checkVerifyStatus File: ../scoreboard/CheckDetection_dpi_pkg.sv Line: 384
# UVM_INFO verilog_src/uvm-1.1d/src/base/uvm_objection.svh(1267) @ 650000: reporter [TEST_DONE] 'run' phase is ready to proceed to the 'extract' phase
# ** Info: Instance coverage for verify 'pulsedetector_tb:757', coverpoint 'pass_cp': metric=100.00 (Pass: 13), at_least= 1 ( COVERED)
# Time: 650 us Scope: CheckDetection_dpi_pkg.VerifyInterfaceT.reportVerifyCoverage File: ../scoreboard/CheckDetection_dpi_pkg.sv Line: 406
# ** Info: Instance coverage for verify 'pulsedetector_tb:744', coverpoint 'pass_cp': metric=100.00 (Pass: 11), at_least= 1 ( COVERED)
# Time: 650 us Scope: CheckDetection_dpi_pkg.VerifyInterfaceT.reportVerifyCoverage File: ../scoreboard/CheckDetection_dpi_pkg.sv Line: 406
# ** Info: Overall coverage for CheckDetection_dpi_verify_calls: metric=100.00 ( COVERED)
# Time: 650 us Scope: CheckDetection_dpi_pkg.VerifyInterfaceT.reportVerifyCoverage File: ../scoreboard/CheckDetection_dpi_pkg.sv Line: 413
#
# --- UVM Report Summary ---
#
# ** Report counts by severity
# UVM_INFO : 4
# UVM_WARNING : 0
# UVM_ERROR : 0
# UVM_FATAL : 0
# ** Report counts by id
# [Questa UVM] 2
# [RNTST] 1
# [TEST_DONE] 1
# ** Note: $finish : D:/3rdparty/R2023a/8709182/share/Questasim/Win/win64/../verilog_src/uvm-1.1d/src/base/uvm_root.svh(430)
# Time: 650 us Iteration: 61 Instance: /mw_PulseDetector_top
# End time: 14:22:31 on Jul 17,2024, Elapsed time: 0:00:23
# Errors: 4, Warnings: 2
cd ../../..The HDL simulator waveform shows the timing of the DUT interface signals. The cursor is placed at a frame boundary and shows the instantaneous update of the matched filter coefficients.
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