uvmbuild
Generate UVM testbench from Simulink model
Add-On Required: This feature requires the ASIC Testbench for HDL Verifier add-on.
Description
uvmbuild(
generates a SystemVerilog top module, which includes a universal verification methodology
(UVM) testbench and a behavioral design under test (DUT). The UVM testbench includes a
sequence, a scoreboard, monitors, and drivers. The dut
,sequence
,scoreboard
)uvmbuild
function
maps:
The Simulink® DUT subsystem to a generated SystemVerilog DPI behavioral DUT
The Simulink sequence subsystem to a UVM sequence block
The Simulink scoreboard subsystem to a UVM scoreboard
uvmbuild(___,
specifies options
using one or more name-value pair arguments in addition to the input arguments in the
previous syntax. For example, Name,Value
)'Driver','mySLTopModule/myDriver'
generates
a UVM driver from the Simulink subsystem specified as 'mySLTopModule/myDriver'
.