uvmcodegen.uvmconfig
Add-On Required: This feature requires the ASIC Testbench for HDL Verifier add-on.
Description
The uvmcodegen.uvmconfig
object is a universal verification methodology
(UVM) configuration object. Use this object to configure UVM generation options such as the
HDL simulation timescale.
Creation
Description
creates a
default UVM configuration object that configures parameters for generated SystemVerilog
code.cfgUvm
= uvmcodegen.uvmconfig
sets properties using one or more name-value pair arguments. Enclose each property name in
quotes. For example, cfgUvm
= uvmcodegen.uvmconfig(Name,Value
)uvmcodegen.uvmConfig('timescale','1ps/1ps')
specifies a UVM configuration object with a timescale signature of one picosecond for the
time unit and one picosecond for the HDL simulation precision.
Properties
Examples
Version History
Introduced in R2020b