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Customize Generated UVM Code

This example uses:

Customize SystemVerilog File Banner

When using the uvmbuild function to generate a UVM testbench, the generated SystemVerilog files have a default file banner. The default banner includes the file location, the date and time that the file was created, and the MATLAB® and HDL Verifier™ versions that the file was created with.

You can customize the generated SystemVerilog files with text or these optional tokens by inserting them inside comment statements in the banner.

  • %<Date> – Date the file was generated (taken from computer clock)

  • %<FileName> – Name of the generated file

  • %<FilePath> – Full path to the location of the generated file

  • %<HDLV_Ver> – HDL Verifier version that created the file

  • %<MATLAB_Ver> – MATLAB version that created the file

  • %<ModelName> – Name of the model

  • %<ModelVersion> – A serial number, incremented by 1 each time you save the model

  • %<LastModifiedDate> – Date when the model was last saved (from Last saved on field on the Model Properties dialog box)

Customize Banner in Subsystem Description

To customize a banner in SystemVerilog components that are mapped from a Simulink® subsystem (for example, sequence or scoreboard subsystems), right-click the Simulink subsystem and select Properties. In the Properties dialog box, click the General tab and, in the Description pane, enter your custom text. For example:

This is my custom banner
%<Date>
%<HDLV_Ver>
For this example, after executing the uvmbuild function, the generated SystemVerilog presents this banner:
//This is my custom banner
//2020-05-08 15:06:16
//HDL Verifier 6.1

Alternatively, you can set the Description parameter by using the set_param (Simulink) function. For example, to set a custom banner for a scoreboard subsystem named scr, execute the following commands:

custom_banner = sprintf('This is my scoreboard\nFile path: %%<FilePath>');
set_param(scr,'Description',custom_banner);
uvmbuild(dut,seq,scr,'Driver',drv,'Monitor',mon);

Customize Banner in Top Model

To customize a banner in the top-level model or in SystemVerilog components that are not mapped to a Simulink subsystem (for example, agent or environment), set the Description parameter in the top Simulink model. On the Simulink toolstrip, click the Modeling tab, and then click Model Explorer. In the Model Properties pane on the right, click the Description tab and enter your custom banner text. In the generated SystemVerilog files, this text appears in the top-model files and the SystemVerilog files in the uvm_testbench/uvm_artifacts folder, which are not mapped to a specific subsystem in Simulink.

Alternatively, you can set the top-model Description parameter by using the set_param (Simulink) function. For example, to set a custom banner for a top model named top, execute the following:

set_param('top','Description','This is a top level comment')
uvmbuild(dut,seq,scr,'Driver',drv,'Monitor',mon);

Customize HDL Simulation Timescale

By default, when the uvmbuild function generates a UVM testbench, the HDL simulation timescale is configured to `timescale 1ns/1ns. You can customize the timescale to a different value by creating a uvmcodegen.uvmconfig configuration object, and then using that UVM configuration object in the uvmbuild function, as in this example:

cfg = uvmcodegen.uvmconfig('timescale','1ps/1ps');
uvmbuild(dut,seq,scr,'Config',cfg);

See Also

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