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测试模型组件

管理组件测试数据,在 SIL 或 PIL 仿真中执行测试套件,配置 Model Verification 模块

在模型中分析和仿真引用模型、子系统或原子子图。将子系统或引用模型提取到框架模型中,从而将其隔离以进行测试。根据您为模块指派的设定,在仿真期间监视模型中的时域信号。构造信号验证,并根据仿真输入组有选择地应用它们。

模块

Assertion检查信号是否为零
Check Dynamic GapCheck that gap of possibly varying width occurs in range of signal's amplitudes
Check Dynamic Lower BoundCheck that one signal is always less than another signal
Check Dynamic RangeCheck that signal falls inside range of amplitudes that varies from time step to time step
Check Dynamic Upper BoundCheck that one signal is always greater than another signal
Check Input ResolutionCheck that input signal has specified resolution
Check Static GapCheck that gap exists in signal's range of amplitudes
Check Static Lower BoundCheck that signal is greater than (or optionally equal to) static lower bound
Check Static RangeCheck that signal falls inside fixed range of amplitudes
Check Static Upper BoundCheck that signal is less than (or optionally equal to) static upper bound

主题

Component Verification

Strategies for verifying functional units of your model, in isolation or in the context of a larger system.

Construct Simulation Tests by Using the Verification Manager

Simulink® Model Verification library blocks assess time-domain signals in your model, according to the specifications that you assign to the blocks.