sldvcombinetests

Combines Simulink Design Verifier test generation results from multiple sessions into one result, even if the model changes

Since R2026a

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Syntax

mergedSldvData = sldvcombinetests(sldvData1...,sldvDataN)

Description

mergedSldvData = sldvcombinetests(sldvData1...,sldvDataN) combines the test generation results into a single result structure.

The sldvcombinetests function aggregates results from multiple test generation analysis sessions into a single data file. It processes input result files to assign a suitable status value and, when possible, a test case for each coverage objective in the final data. If multiple test cases exist for a given objective, sldvcombinetests selects one of them.

sldvcombinetests allows few permissible changes to model semantics across multiple analysis runs. For example, changing parameter configuration is allowed but not the model contents across runs.

Note

The sldvmergedata lets you merge results, including dead logic status, when model semantics remain unchanged across runs.

example

Examples

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Open Live Script

Merge test generation results for the model mState_machine after modifying the model.

Open the example. Set up test generation options for decision coverage.

model = "mState_Machine";
open_system(model);
opts = sldvoptions;
opts.MaxProcessTime = 60;
opts.Mode = "TestGeneration";
opts.ModelCoverageObjectives = "Decision";
[~,fileNames1,errors] = sldvrun(model,opts);

Use the generated results to generate a coverage file.

runOpts = sldvruntestopts;
runOpts.coverageEnabled = true;
[~,covData] = sldvruntest(model,fileNames1.DataFile,runOpts);
covFileName = "mState_Machine_Param_cov.cvt";
cvsave(covFileName,covData);

Use the coverage file to top-off coverage for the next run.

opts.ModelCoverageObjectives = "ConditionDecision";
opts.IgnoreCovSatisfied = "on";
opts.CoverageDataFile = covFileName;

Modify the model by updating the OutMin and OutMax parameters.

set_param("mState_Machine/Cell_Temperatures","OutMin","300");
set_param("mState_Machine/Cell_Temperatures","OutMax","300");

To restrict the value generated by Simulink Design Verifier, add an Assumption block to the model and set the value for the 'Pack_Voltage' input to 4.

set_param("mState_Machine/Cell_Voltages","OutMin","4")
set_param("mState_Machine/Cell_Voltages","OutMax","4")

Run Simulink Design Verifier again with the updated options.

[~,fileNames2] = sldvrun(model,opts);

Combine the analysis results.

sldvData = sldvcombinetests(fileNames1.DataFile,fileNames2.DataFile);

You can also save the merged data.

mergedDataFile = "mState_Machine_sldv_merged.sldvData";
save(mergedDataFile,"sldvData");

Input Arguments

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Name of the data file that contains the analysis results, specified as a character vector or string scalar.

Example: mState_Machine_Merged.sldvData

Output Arguments

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Merged results containing the test cases, returned as a structure.

Limitations

  • You can merge only test generation results. Merging results from different analysis modes such as detecting design errors and property proving is not supported.

Version History

Introduced in R2026a

See Also

| (Simulink Coverage) | (Simulink Coverage) | (Simulink Coverage) | | |