Prepare and Analyze Model

Identify analyzable components for unit or system-level testing, address model incompatibilities or analysis timeout

Use Simulink^® Design Verifier™ to guide the design process as you build your model. Avoid potential bugs by running analyses iteratively as you update your model. If you already have an existing design in Simulink, configure portions of your design for Simulink Design Verifier analysis.

If you have an existing model, subsystem, or subchart in Simulink, configure portions of your design for Simulink Design Verifier analysis. Use the bottom-up approach, analyzing smaller components first, for best results with a large or complex model.

Model Analysis Basics

Featured Examples

Simulate Harness Model with Signal Editor Inputs Block

Generate model coverage report by simulating the test harness model with the Signal Editor Inputs block. You can simulate a single test case or counterexample by selecting the active scenario in the Signal Editor dialog box. For more information see, Simulate Harness Model by Using the Signal Editor Inputs Block.

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Test Condition Block

Constrain input values. The Test Condition block forces the input value to be either 0 or 1.

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Test Objective Block

The use of two custom Test Objective blocks. The block "True" forces the output signal to be 2. The block "Edge" inside "Masked Objective" specifies that the output signal transition from 2 to 1.

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Use Observer Reference Block for Test Case Generation

Generate test cases using Observer Reference blocks.

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Generate Parameters Values

Tune parameters using parameter configuration file for Simulink® Design Verifier™ analysis. The model contains the parameter control_mode that enables the active controller and selects its output to be the model output. Simulink Design Verifier treats this parameter as an input that is constrained to be either 1 or 2 and generates the appropriate value for each test case.

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Debounce Temporal Properties

Model temporal system requirements for property proving and test case generation using Simulink® Design Verifier™ Temporal Operator blocks.

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Power Window Controller Temporal Properties

Model temporal system requirements in a power window controller model for property proving and test case generation using Simulink® Design Verifier™ Temporal Operator blocks.

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