Simulink Design Verifier 分析的最佳做法

Simulink^® Design Verifier™ 分析的最佳做法、注意事项和支持限制

Simulink Design Verifier 为 Simulink 功能提供不同级别的支持。如果您的模型包含部分支持的模块，您可以启用自动插桩或避免在您分析的模型中使用不支持的功能。

主题

Simulink Design Verifier Block Library
Accessing the Simulink Design Verifier block library.
Handle Incompatibilities with Automatic Stubbing
How to use automatic stubbing.
Modified Condition and Decision Coverage in Simulink Design Verifier
Describes the difference between MCDC coverage in Simulink Design Verifier and in Simulink Coverage™.
Enhanced MCDC Coverage in Simulink Design Verifier
Describes the Enhanced MCDC coverage concept and workflows.
Logical Operations Short-circuiting
Explains how Simulink Design Verifier short-circuits logic blocks.
How Simulink Design Verifier Reports Approximations Through Validation Results
Describes how Simulink Design Verifier reports approximations through validation results.

Support Limitations for Simulink Software Features
Lists Simulink software features that Simulink Design Verifier does not support.
Supported and Unsupported Simulink Blocks in Simulink Design Verifier
Lists Simulink blocks that Simulink Design Verifier does and does not support.
Support Limitations for Model Blocks
Simulink Design Verifier supports the Model block with some limitations.
Support Limitations for Stateflow Software Features
Lists the Stateflow^® software features that the Simulink Design Verifier and Fixed-Point Designer™ software does not support.
Support Limitations for MATLAB for Code Generation
Lists limitations associated with Simulink Design Verifier software support for MATLAB^® for code generation.
Support Limitations and Considerations for S-Functions and C/C++ Code
Describes limitations and considerations of S-functions and Generated Code in Simulink Design Verifier.
Nonfinite Data
Simulink Design Verifier does not support nonfinite data (for example, NaN and Inf) and related operations.
Counters and Timers
Best practices for handling counters and timers in your model to avoid over complicating Simulink Design Verifier analysis.
Logical Operations
If you have a Simulink model with both logical and arithmetic operations, consider analyzing only the logical operations.