Best Practices for Simulink Design Verifier Analysis

Best practices, considerations, and support limitations for Simulink^® Design Verifier™ analysis

Simulink Design Verifier provides various levels of support for the Simulink features. If your model contains partially-supported blocks, you can enable automatic stubbing or avoid using unsupported features in models that you analyze.

Topics

Best Practices and Considerations

Simulink Design Verifier Block Library
Accessing the Simulink Design Verifier block library.
Handle Incompatibilities with Automatic Stubbing
How to use automatic stubbing.
Modified Condition and Decision Coverage in Simulink Design Verifier
Describes the difference between MCDC coverage in Simulink Design Verifier and in Simulink Coverage™.
Enhanced MCDC Coverage in Simulink Design Verifier
Describes the Enhanced MCDC coverage concept and workflows.
Analyze Model for Enhanced MCDC Analysis
Analyze a model for enhanced MCDC objectives.
Logical Operations Short-circuiting
Explains how Simulink Design Verifier short-circuits logic blocks.
How Simulink Design Verifier Reports Approximations Through Validation Results
Describes how Simulink Design Verifier reports approximations through validation results.

Support Limitation Details

Support Limitations of Simulink Design Verifier for Simulink Software Features
Lists Simulink software features that Simulink Design Verifier does not support.
Supported and Unsupported Simulink Blocks in Simulink Design Verifier
Lists Simulink blocks that Simulink Design Verifier does and does not support.
Support Limitations for Model Blocks
Simulink Design Verifier supports the Model block with some limitations.
Support Limitations for Stateflow Software Features
Lists the Stateflow^® software features that the Simulink Design Verifier and Fixed-Point Designer™ software does not support.
Support Limitations for MATLAB for Code Generation
Lists limitations associated with Simulink Design Verifier software support for MATLAB^® for code generation.
Support Limitations and Considerations for S-Functions and C/C++ Code
Describes limitations and considerations of S-functions and Generated Code in Simulink Design Verifier.
Nonfinite Data
Simulink Design Verifier does not support nonfinite data (for example, NaN and Inf) and related operations.
Counters and Timers
Best practices for handling counters and timers in your model to avoid over complicating Simulink Design Verifier analysis.
Logical Operations Short-circuiting
Explains how Simulink Design Verifier short-circuits logic blocks.