降低模型复杂度
使用自下而上的方法分析大型模型,定义模块替换规则
Simulink® Design Verifier™ 软件在分析大型模型时,采用自下而上的方法最有效。在这种方法中,软件首先分析较小的模型组件,这可能比使用默认设置更快。自下而上的方法具有以下几个优势:
它让您可以在受控环境中解决使错误检测、测试生成或属性证明的速度变慢的问题。
在分析整个模型之前先解决小模型组件的问题会更高效,尤其是当模型中有无法访问且只能在模型上下文中发现的组件时。
您可以更快地进行调试,以迭代方式查找和修复问题。
如果单个模型组件存在问题(例如,在仿真中无法访问某个组件),则可能会阻止该软件为大型模型中的所有目标生成测试。
如果要解决模型中的兼容性限制或自定义模型元素以进行分析,您可以使用 Simulink Design Verifier 模块替换规则。如果要在分析过程中为模型中的参数生成其他值,可使用 Simulink Design Verifier 参数配置。
函数
sldvblockreplacement | Replace blocks for analysis |
主题
降低模型复杂度
- Bottom-Up Approach to Model Analysis
Explains the benefits of analyzing a model starting with low-level elements. - Sources of Model Complexity
Describes model characteristics that may complicate an analysis. - Role of Approximations During Model Analysis
Approximations Simulink Design Verifier performs before beginning its analysis. - Logical Operations
If you have a Simulink model with both logical and arithmetic operations, consider analyzing only the logical operations. - Model Blocks
Analyzing Model blocks that reference external models. - Extract Subsystems for Analysis
Explains how subsystems and atomic subcharts are extracted for individual analysis. - Manage Model Data to Simplify the Analysis
Simplify your model to simplify the Simulink Design Verifier analysis. - Partition Model Inputs for Incremental Test Generation
You can constrain the values of model inputs using the Simulink Design Verifier Test Condition block. - Analyzing Models with Large Verification State Space
Techniques to simplify the complexity of models with large verification state spaces. - Block Reduction
Explains how Simulink reduces blocks during simulation and how it affects the Simulink Design Verifier analysis.
执行模块替换
- What Is Block Replacement?
Brief overview of block replacements. - Built-In Block Replacements
Describes the factory default block replacement rules and library. - Template for Block Replacement Rules
Introduces a template for creating custom block replacement rules. - Block Replacements for Unsupported Blocks
This example shows how to use Simulink® Design Verifier™ functions to replace unsupported blocks and how to customize test vector generation for specific requirements.