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Analyze Test Harness with Schedule for Initialize, Reset, Reinitialize, and Terminate Functions

Since R2024b

When you have an export function model containing Initialize, Reinitialize, Reset, and Terminate Function blocks and a scheduler harness for the model under test, you can perform:

  • Design error detection analysis

  • Test generation analysis

  • Quality analysis on the model by running the model advisor checks with Simulink® Design Verifier™ checks

When you perform design error detection analysis on such a model, Simulink Design Verifier shows an incompatibility that says that the model contains Reinitialize Function or Reset Function blocks that Simulink Design Verifier does not support.

To address this incompatibility, generate a test harness that provides a schedule for calling reinitialize or reset functions. You can then analyze the harness model containing explicit entry points. For more information, see Create Test Harness to Generate Function Calls.

Generate Test Cases for Model with Initialize Function, Reset Function, and Terminate Function Blocks

Open Live Script

This example shows how you can generate tests for a test harness that models an event scheduler to trigger execution of Initialize Function, Reset Function, and Terminate Function block contents.

Model Description

The model sldvExportFcnIRTScheduler simulates function-call events. The sldvExportFcnIRT model is referenced by a Model block in the sldvExportFcnIRTScheduler model. The event scheduler, modeled using Stateflow® charts, generates function-call events, driving the model's execution. The Initialize Function and Reset Function blocks read Discrete-Time Integrator block states from the NVRAM data store, and the Terminate Function block writes these states to the data store.

Open the model sldvExportFcnIRTScheduler.

open_system('sldvExportFcnIRTScheduler')

irt_example_model.png

Perform Test Generation Analysis

To perform test generation analysis on the model, on Design Verifier tab, in the Analyze section, click Generate Tests.

Simulink Design Verifier generates test cases for the model. The Simulink Design Verifier Results Summary window shows that the test generation completed successfully. For more information on test generation analysis, see What Is Test Case Generation?.

results_summary_irt.png

Review Analysis Results

The sldvExportFcnIRT Model block is highlighted in red, indicating the test cases that satisfy its test objectives. The analysis report shows that one objective is satisfied.

test_generation_analysis_irt.png

Double-click the sldvExportFcnIRT subsystem to view the Initialize Function, Reset Function, and Terminate Function blocks after the analysis.

sldv_export_function_irt.png

To access the detailed analysis report, click HTML in the Results window.

Limitations

Simulink Design Verifier does not support analysis of a test harness that schedules the execution of Initialize Function, Reset Function, Reinitialize Function, and Terminate Function blocks when you:

  • Perform enhanced MCDC or property proving analysis.

  • Use instance-specific parameters.

  • Use a model block which refers to a rate-based model reference and has Initialize, Reset, Reinitialize, and Terminate ports enabled.

  • Use a harness model which contains Observer Reference blocks.

  • Use a harness model which has multiple model blocks at the root level.

  • Use a model reference that contains:

    • Variable size inputs.

    • Function call subsystems with unconnected trigger port in its model reference hierarchy.

    • Simulink Function block with inports and outports in its model reference hierarchy.

    • Stateflow® graphical function.

    • Input or output signals connected to signals from parent model with different dimension via signal routing blocks such as Mux, Demux, and Vector Concatenate.

  • Perform analysis using these design error detection checks:

    • Check usage of rem and reciprocal operations

    • Check usage of Sqrt operations

    • Check usage of Reciprocal Sqrt blocks

    • Check usage of log and log10 operations

    • Non-finite and NaN floating-point values

    • Subnormal floating-point values

    For more information on design error detection checks, see Simulink Design Verifier Checks.

Note

Simulink Design Verifier analysis ignores the behavior of Reset, Reinitialize or Terminate subsystems if they do not receive a function-call event signal from the corresponding event port.

See Also