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Interprocess Data Channel

Model interprocessor data channel between two processors

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  • Library:

  • SoC Blockset / Processor Interconnect

  • Block icon of interprocess data channel.

Description

The Interprocess Data Channel block simulates the interprocessor data channel available in multiprocessor or OS managed SoC hardware board families. The block provides a channel for asynchronous data transfer between two processors. This diagram shows a generalized view of the interprocessor data connection.

Limitations

In an SoC model, when Interprocess Data Channel blocks form a closed-loop between two or more tasks, it can create an artificial algebraic loop for the Simulink® solver. To break the loop, the Simulink solver implicitly adds a delay into the loop. This delay is related to an internal event and cannot be modified by the user, but the delay typically will be on the same order as the base time-step of the model. For more information on artificial algebraic loops in Simulink solvers, see Artificial Algebraic Loops.

Ports

Input

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This message port receives input data as a message from a connected Interprocess Data Write block. For more information on messages, see Messages.

Data Types: SoCData

Output

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This message port sends output data as a message to a connected Interprocess Data Read block. For more information on messages, see Messages.

Data Types: SoCData

This port sends a true signal output whenever an overwrite of the internal buffer queue occurs. When the connected processor model executes in external mode, the connected Interprocess Data Write block generates the overwritten signal in the Simulation Data Inspector tool.

Dependencies

To enable this port, select the Show when buffer is overwritten parameter.

Data Types: Boolean

This port outputs the number of buffers currently in use in the block's internal buffer queue. When the connected processor model executes in external mode, the connected Interprocess Data Write block generates the used signal in the Simulation Data Inspector tool.

Dependencies

To enable this port, select the Show number of used buffers parameter.

Data Types: Boolean

This port sends a task event signal that triggers the Task Manager block to execute the associated event-driven task.

Note

For TI’s C2000™ hardware boards, when the Interprocess Data Channel block connects to the Task Manager block, the allowed interrupts available in the Hardware Mapping tool must be in consecutive order starting from IPC0. For example:

  • If one Interprocess Data Channel block is in the model, then only IPC0 interrupt is allowed

  • If two Interprocess Data Channel blocks are in the model, the only IPC0 and IPC1 interrupts are allowed.

Dependencies

To enable this port, select the Show event port parameter.

Data Types: rteEvent

Parameters

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Number of buffers making up the storage system.

Specify the propagation delay of data transfers through the this block. To ignore propagation delays, set this parameter to 0.

Enable an event port that, when connected to the Task Manager block, can execute event-driven tasks.

Enable an output port that shows the current number of buffers used in the Interprocess Data Channel block internal buffer queue.

Enable an output port that signals when a overwrite of the Interprocess Data Channel block internal buffer queue occurred.

Model Examples

One Way Interprocess Communication

One Way Interprocess Communication

One-way interprocess data communication between two bare metal processors.

Open Script
Two Way Interprocess Communication

Two Way Interprocess Communication

Two-way interprocess data communication between two processors running in an operating system managed processor.

Open Model
Partition Motor Control for Multiprocessor MCUs

Partition Motor Control for Multiprocessor MCUs

Partition real-time motor control application on to multiple processors to achieve design modularity and improved control performance.

Open Example

Version History

Introduced in R2020b

See Also

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