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Video Capture MIPI

Import live video frames from MIPI CSI-2 card on Zynq-based hardware

Since R2022b

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Add-On Required: This feature requires the SoC Blockset Support Package for AMD FPGA and SoC Devices add-on.

  • Video Capture MIPI block

Libraries:
SoC Blockset Support Package for AMD FPGA and SoC Devices / MPSoC / ZCU106

Description

The Video Capture MIPI block captures video frames from an IMX274 FMC MIPI® CSI-2® card connected to a Zynq®-based board and imports the frames into your Simulink® model. The reference design programs the FPGA with an image that demosaics and gamma-corrects the video input from the sensor, and allows capture of the video from Simulink. You can control the frame size and Simulink video signal format options from the Video Capture MIPI block.

The FPGA image also contains an IP core called the FPGA user logic that you can generate from your design by using HDL Workflow Advisor. The block captures the input video after the FPGA user logic.

The video data is in AXI4-Stream Video format on the FPGA. When you import the video into Simulink, the stream converts to frame-based video.

The MIPI Receive path reference design requires the same video resolution and color format for the entire data path. The design you target to the FPGA user logic must not modify the frame size or format of the data.

Examples

Getting Started with MIPI Sensor

Getting Started with MIPI Sensor

Get started with MIPI® CSI-2® video capture and processing by using SoC Blockset™ Support Package for AMD® FPGA and SoC Devices.

Corner Detection with Zynq-Based Hardware and MIPI Sensor

Corner Detection with Zynq-Based Hardware and MIPI Sensor

Target a corner detection algorithm to a ZCU106 device with a MIPI® add-on card by using the SoC Blockset™ Support Package for AMD® FPGA and SoC Devices.

Limitations

  • To use this block, in the hardware setup, set Hardware Board to Xilinx Zynq UltraScale+ MPSoC ZCU106 Evaluation Kit and set Add-on Card to IMX274MIPI-FMC.

  • Use the IP core workflow to generate HDL code. This block does not support using the SoC Builder tool. For more information on workflows, see SoC Generation Workflows.

    In the HDL Workflow Advisor tool, in step 1.1, set Target platform to ZCU106 IMX274MIPI-FMC. In step 1.2, set Reference design to MIPI Receive path.

    You can also use the HDL Workflow Advisor to generate a software model for running in external mode.

Ports

Output

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The block returns one matrix for each color component of the input video. The dimensions of each matrix match the frame size.

Dependencies

To enable these ports, set Pixel format to RGB and Image signal to Separate color signals.

Data Types: single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | Boolean | fixed point

The block returns a 3-by-height-by-width matrix, where height and width match the frame size.

Dependencies

To enable this port, set Pixel format to RGB and Image signal to One multidimensional signal.

Data Types: single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | Boolean | fixed point

Parameters

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The video stream originates from the IMX274 camera board. Set the Frame size parameter to match the resolution of your attached camera.

Select 720p HDTV format (1280x720p) or 1080p HDTV format (1920x1080p).

The block sets the Simulink sample time for the captured video frames to 1/Frame rate.

Frame size 1920x1080p supports only 60 fps.

The RGB pixel stream format returns three 8-bit color components per pixel, which is 24 bits per pixel total. You can also select whether the block returns a multidimensional signal or three separate color signals. For details, see the Image signal parameter.

Specify the RGB output stream format as one of these values.

  • Separate color signals — The block returns separate height-by-width matrices for each color component. In this case, the block has R, G, and B output ports.

  • One multidimensional signal — The block returns a single 3-by-height-by-width matrix. In this case, the block has an Image output port.

Version History

Introduced in R2022b

See Also

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