Deploy IP Core With Auto-Generated Reference Design

R2026b
Since R2026b

Deploying a MATLAB® or Simulink® algorithm to an FPGA or SoC requires a reference design. A reference design defines how your generated IP core integrates into a complete system. For example, a reference design can define connections to the processor, clock and reset signals, board peripherals, and other IP cores.

For some boards, MathWorks® or hardware vendors provide reference designs that you can use without change. You can also author your own custom reference design by using an external design tool such as AMD® Vivado® IP integrator and register it with HDL Coder™. Authoring a custom reference design requires FPGA design tool expertise, knowledge of the target board architecture, and setup time.

Alternatively, if no reference design exists for your board or system requirements, you can have HDL Coder generate a reference design for you. Set the Reference Design parameter to Auto-generated, map your algorithm ports to the interfaces you need, and HDL Coder builds a complete, deployable system that includes your generated IP core.

This table compares reference design approaches and when to use each one.

ApproachDescriptionWhen to Use
Use a pre-authored reference design supplied by MathWorks or a vendor, or a custom reference designYou must map your ports to the fixed interfaces provided by the reference design. HDL Coder integrates the generated IP core into the system as-is.

The automatically generated reference design does not meet your system requirements. For example, your design needs interfaces that the automatically generated system does not support, or your system might require additional customization beyond what is available through the automatically generated reference design.

Use an automatically generated reference designYou can map your ports to the interfaces your algorithm needs. HDL Coder generates a complete hardware system based on your interface mappings.When you do not have FPGA design tool experience and no pre-authored reference design is available for your board, or you want to tailor the system to your algorithm.

Prerequisites

To deploy an IP core with an automatically generated reference design, you must:

  • Install HDL Coder and SoC Blockset™ for AMD.

  • Set the synthesis tool to AMD Vivado.

  • Target an AMD Zynq® UltraScale+™ MPSoC or RFSoC board. For example, ZCU102, ZCU111, or ZCU216.

    If you are using a custom board that belongs to an AMD Zynq UltraScale+ MPSoC or RFSoC board family, you must create and register a custom board definition and provide a VivadoBoardPart (HDL Coder) number. For more information, see Register a Custom Board (HDL Coder).

  • Set the Target workflow configuration parameter to IP Core Generation.

Limitations

When deploying an IP core with an automatically generated reference design, HDL Coder does not support:

  • AMD Zynq and Versal, Altera®, and Microchip platforms.

  • AXI4-Stream, AXI4-Stream Video, AXI4 Master, FPGA Data Capture, and JTAG AXI Manager interfaces.

  • RF Data Converter (RFDC) interfaces for RFSoC platforms.

  • The high-level synthesis (HLS) IP core workflow.

Generated Output

When you select an automatically generated reference design, this table lists the generated artifacts, their description, and their location. The generated hardware system depends on the specified interface mappings.

OutputDescriptionArtifact Location
IP coreGenerated IP core<ProjectFolder>\ipcore
FPGA block designProcessor, interconnects, clock management, and generated IP core<ProjectFolder>\vivado_ip_prj
Device treeLinux device tree nodes that enable the operating system to discover and communicate with the deployed IP core after boot<ProjectFolder>\devicetree
Software interface modelSimulink model for reading registers, writing parameters, and streaming data to and from the deployed hardwaregm_<ModelName>_interface.slx
Host interface scriptsMATLAB scripts for interacting with the running hardware from the command line, including testing, data capture, and integrationgs_<ModelName>_interface.m and gs_<ModelName>_setup.m

Generate and Deploy an IP Core Using an Automatically Generated Reference Design

In this example, you generate and deploy an IP core by using an automatically generated reference design. You generate the IP core interactively by using the IP Core Editor, then programmatically at the command line.

To run this example, you must install and set up this software and hardware:

  • SoC Blockset (for AMD)

  • SoC Blockset Support Package for AMD FPGA and SoC Devices

  • AMD Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit

To set up the hardware board and install the support package, see Installation and Setup.

To run the example by using the HDL Coder Workflow Advisor, see Comparison of IP Core Generation Techniques (HDL Coder).

Open the Model

Open the hdlcoder_led_blinking model. The design under test (DUT) is the subsystem led_counter, which models a counter that blinks the LEDs on an FPGA board. The two input ports, Blink_frequency and Blink_direction, control the LED blink frequency and direction. The output port LED connects to the LED hardware on the board. The output port Read_Back reads data back to the processor.

open_system("hdlcoder_led_blinking");

Generate and Deploy IP Core

You can generate and deploy an IP core interactively by using the HDL Coder app and the IP Core Editor (HDL Coder) or programmatically by using the hdlcoder.WorkflowConfig (HDL Coder) object and the hdlcoder.runWorkflow (HDL Coder) function.

Generate and Deploy IP Core by Using the HDL Coder App and IP Core Editor.  To generate and deploy an IP core using the HDL Coder app and IP Core Editor:

  1. In the Apps tab, click HDL Coder.

  2. In the HDL Code tab, set the button in the Output section to IP Core.

  3. Click Settings. In the Configuration Parameters dialog box, set the Target platform to an AMD Zynq UltraScale+ MPSoC or RFSoC evaluation board. For example, set the Target platform to Xilinx Zynq UltraScale+ MPSoC ZCU102 evaluation kit. Set the Reference Design to Auto-generated.

  4. Set Target Frequency to 50.

  5. Click OK to save your updated settings.

  6. Configure the interface mappings. In the IP Core pane, select the Interface Mapping tab.

    1. To compile your model and repopulate the DUT ports and their data types in the target platform interface table, click the Reload IP core settings Reload button depicted as a green arrow pointing to the right button.

    2. For the ports Blink_frequency, Blink_direction, and Read_back, set the cells in the Interface column to AXI4-Lite.

    3. For the LED output port, set the cell in the Interface column to LEDs General Purpose [0:7].

    4. Validate the settings by clicking the Validate IP core settings Validate button depicted as a green check mark button.

  7. On the HDL Code tab of the Simulink Toolstrip, click Generate IP Core to generate an IP core.

  8. Create a Vivado project. In the HDL Code tab, select Build Bitstream > Create IP Core Project.

  9. Generate the software interface model. In the HDL Code tab, select Build Bitstream > Software Interface Model.

  10. To specify the operating system for the software model, select Build Bitstream > Deployment Settings, and specify the project-related settings in the Generate Software Interface section.

  11. Generate the host interface script. In the HDL Code tab, select Host Interface Script > Host Interface Script. To specify the target interface, in the Host target interface section, select Ethernet.

  12. Build the bitstream. In the HDL Code tab, click Build Bitstream. To specify the options related to bitstream build, select Build Bitstream > Deployment Settings, and specify the bitstream-related settings in the Build Bitstream section.

  13. Deploy the IP core. In the HDL Code tab, select Build Bitstream > Program Target Device. To specify the program target device settings, select Build Bitstream > Deployment Settings, and configure the settings in the Program Target Device section. After deployment, use the generated software interface or host scripts to interact with your hardware from MATLAB.

Generate and Deploy IP Core Programmatically.  To generate and deploy an IP core by using the hdlcoder.WorkflowConfig object and hdlcoder.runWorkflow function:

  1. Set up the path to the synthesis tool by using the hdlsetuptoolpath (HDL Coder) function.

    hdlsetuptoolpath("ToolName","Xilinx Vivado","ToolPath","C:\Xilinx\Vivado\2025.1.1\bin\vivado.bat")

  2. Verify the design behavior by opening and simulating the model.

    open_system("hdlcoder_led_blinking");
sim("hdlcoder_led_blinking");

  3. Set the workflow to IP Core Generation and set the target DUT subsystem to hdlcoder_led_blinking/led_counter. Configure the target platform and synthesis tool. Set the target frequency to 50 MHz.

    hdlset_param("hdlcoder_led_blinking", "Workflow", "IP Core Generation");
hdlset_param("hdlcoder_led_blinking", "HDLSubsystem", "hdlcoder_led_blinking/led_counter");
hdlset_param("hdlcoder_led_blinking", "ProjectFolder", "hdl_prj");
hdlset_param("hdlcoder_led_blinking", "ResetType", "Synchronous");
hdlset_param("hdlcoder_led_blinking", "SynthesisTool", "Xilinx Vivado");
hdlset_param("hdlcoder_led_blinking", "SynthesisToolChipFamily", "Zynq UltraScale+");
hdlset_param("hdlcoder_led_blinking", "SynthesisToolDeviceName", "xczu9eg-ffvb1156-2-e");
hdlset_param("hdlcoder_led_blinking", "SynthesisToolPackageName", "");
hdlset_param("hdlcoder_led_blinking", "SynthesisToolSpeedValue", "");
hdlset_param("hdlcoder_led_blinking", "TargetDirectory", "hdl_prj\hdlsrc");
hdlset_param("hdlcoder_led_blinking", "TargetFrequency", 50);
hdlset_param("hdlcoder_led_blinking", "TargetPlatform", "Xilinx Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit");
hdlset_param("hdlcoder_led_blinking", "Traceability", "on");

    Set the reference design to Auto-generated.

    hdlset_param("hdlcoder_led_blinking", "ReferenceDesign", "Auto-generated");

  4. Map each DUT port to its target interface. Map the control and read-back ports to AXI4-Lite and the LED output to the target board LEDs.

    hdlset_param('hdlcoder_led_blinking/led_counter/Blink_frequency', 'IOInterface', 'AXI4-Lite');
hdlset_param('hdlcoder_led_blinking/led_counter/Blink_frequency', 'IOInterfaceMapping', 'x"100"');
hdlset_param('hdlcoder_led_blinking/led_counter/Blink_direction', 'IOInterface', 'AXI4-Lite');
hdlset_param('hdlcoder_led_blinking/led_counter/Blink_direction', 'IOInterfaceMapping', 'x"104"');

hdlset_param('hdlcoder_led_blinking/led_counter/LED', 'IOInterface', 'LEDs General Purpose [0:7]');
hdlset_param('hdlcoder_led_blinking/led_counter/LED', 'IOInterfaceMapping', '[0:7]');
hdlset_param('hdlcoder_led_blinking/led_counter/Read_back', 'IOInterface', 'AXI4-Lite');
hdlset_param('hdlcoder_led_blinking/led_counter/Read_back', 'IOInterfaceMapping', 'x"108"');

  5. Create a hdlcoder.WorkflowConfig object and enable:

    • Project creation

    • IP core and IP core report generation

    • Bitstream build and generation

    • Software interface model and host script generation

    hWC = hdlcoder.WorkflowConfig("SynthesisTool","Xilinx Vivado","TargetWorkflow","IP Core Generation");
hWC.ProjectFolder = "hdl_prj";
hWC.ReferenceDesignToolVersion = "*";
hWC.IgnoreToolVersionMismatch = false;

hWC.RunTaskGenerateRTLCodeAndIPCore = true;
hWC.RunTaskCreateProject = true;
hWC.RunTaskGenerateSoftwareInterface = true;
hWC.RunTaskBuildFPGABitstream = true;
hWC.RunTaskProgramTargetDevice = false;


hWC.GenerateIPCoreReport = true;

hWC.Objective = hdlcoder.Objective.None;
hWC.AdditionalProjectCreationTclFiles = "";
hWC.EnableIPCaching = false;

hWC.GenerateSoftwareInterfaceModel = true;
hWC.OperatingSystem = "Linux";
hWC.HostTargetInterface = "Ethernet";
hWC.GenerateHostInterfaceModel = false;
hWC.GenerateHostInterfaceScript = true;

hWC.RunExternalBuild = true;
hWC.EnableDesignCheckpoint = false;
hWC.TclFileForSynthesisBuild = hdlcoder.BuildOption.Default;
hWC.CustomBuildTclFile = "";
hWC.DefaultCheckpointFile = "Default";
hWC.RoutedDesignCheckpointFilePath = "";
hWC.MaxNumOfCoresForBuild = "synthesis tool default";

  6. Configure the board connection credentials and program the board by using the generated bitstream. Replace the board IP address and SSH credentials with your target board IP address and credentials.

    hWC.ProgrammingMethod = hdlcoder.ProgrammingMethod.Download;
hWC.IPAddress = "192.168.1.101";
hWC.SSHUsername = "root";
hWC.SSHPassword = "root";

  7. Validate the configuration and generate the IP core by using the hdlcoder.runWorkflow function.

    hWC.validate;
hdlcoder.runWorkflow("hdlcoder_led_blinking/led_counter", hWC);

  8. Interact with the generated IP core by using the generated host interface script and MATLAB.

    hProcessor = xilinxsoc();

hFPGA = fpga(hProcessor);
gs_hdlcoder_led_blinking_setup(hFPGA);

writePort(hFPGA, "Blink_frequency", zeros([1 1]));
writePort(hFPGA, "Blink_direction", zeros([1 1]));
data_Read_back = readPort(hFPGA, "Read_back");

release(hFPGA);

See Also

(HDL Coder) | (HDL Coder) | (HDL Coder)

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