Import HDL IP Core into SoC Model

Use the HDL IP Importer tool to import an existing HDL IP core into an SoC Simulink^® model as a library block. To open the HDL IP Importer tool, in the Simulink toolstrip, on the System on Chip tab, click HDL IP Importer or enter hdlIPImporter at the MATLAB^® command prompt. The tool takes you through the steps to generate a library block.

Note

This workflow supports Xilinx^® devices only.

Enter Block Details
Select HDL IP Source Location
Enter HDL IP Details
Review Block Interfaces
Review Clock and Reset Interfaces
Enter Linux Device Details
Review Summary

Enter Block Details

Enter the block and library details to apply to the generated Simulink block.

Block name — Block name. The default value is myBlock.
Library name — Library name. The tool adds the generated block to this library. The default value is myLibrary.
Library location — Location to which the tool saves the library. The default value is your current MATLAB path.
Allow multiple block instances in a Simulink model — Option to include multiple instances of the generated block in the same Simulink model.

Select HDL IP Source Location

Select the location of the HDL IP source files.

Use HDL IP Catalog — Option to use the Xilinx Vivado^® HDL IP Catalog.
Specify HDL IP source location — Option to use your own HDL IP core repository.
IP location — Location of the HDL IP core repository. To enable this parameter, select Specify HDL IP source location.

Enter HDL IP Details

Enter the details of the HDL IP or top module file.

If the tool finds the IP-XACT file, the tool prompts you to provide the details of the HDL IP.
- IP name (VLNV) — Name of the HDL IP to import as a Simulink block.
If the tool does not find the IP-XACT file, the tool prompts you provide the details of the top module file.
- Top module file — Location of the top module file.
- Module name — Name of the module to import as a Simulink block.
Enter the details of the constraints file.
- Constraints file (.xdc) — Location of the constraints file of the HDL IP core. This is an optional parameter.

Review Block Interfaces

The tool derives the interfaces of the HDL IP core from the IP-XACT file and displays them in a table. If the tool does not find the IP-XACT file, it derives the inputs and outputs from the specified top module file. You can review or update the listed interfaces. The tool adds the HDL IP interfaces as ports to the generated block in the order in which they appear in the table. You can reorder the interfaces by using the Up and Down buttons.

From the IP-XACT file, the tool lists the AXI4-Stream, AXI4-Stream Video, AXI4 Master, and I/O HDL IP interfaces. If you do not want a listed interface as a block port, you can remove the interface by using the Remove button.

From the top module file, the tool lists all the inputs and outputs, including clock and reset. To add the clock and reset interfaces to the next step, remove these interfaces by using the Remove button. If you do not want a listed input or output as a block port, you can remove it by using the Remove button.

Specify data type, dimension, and interface type of the port.

Name — Name of the HDL IP interface that the tool adds as a port to the generated block.
Direction — Direction of the HDL IP interface, which determines the direction of the port in the generated block.
Data type — Data type of the port in the generated block.
Dimension — Dimension of the port in the generated block.
Interface type — Interface type of the port in the generated block.

Review Clock and Reset Interfaces

Review the clock and reset interfaces. Select the required source for these interfaces.

The tool adds the clock and reset interfaces as ports to the generated block.

Name — Name of the HDL IP interface that the tool adds as a port to the generated block.
Type — Type of the HDL IP interface. The interface can be a clock or reset input.
Source — Source that drives the clock and reset interfaces.

Enter Linux Device Details

Enter the device tree file for the HDL IP and pre- and post-load scripts. You can skip this step if the HDL IP does not communicate with the processing system (PS).

Device tree file (.dtsi) — Location of the device tree file for the HDL IP core.
Pre-load script (.m) — Location of the pre-load script. Specify this field to customize the load step in the SoC Builder tool. The pre-load script runs before you program the hardware.
Post-load script (.m) — Location of the post-load script. Specify this field to customize the load step in the SoC Builder tool. The post-load script runs after you program the hardware.

Review Summary

This tool displays the details that it uses to generate the Simulink block. Review the block details and click Generate. To close the tool after successful block generation, click Finish.

In addition to the Simulink block, the tool also generates the editable simulation file libraryName_blockName_sim and the editable customization file libraryName_blockName_customize, where libraryName and blockName are the library and block names, respectively.

libraryName_blockName_sim — Use this M file to provide the behavioral simulation logic for the generated block.
libraryName_blockName_customize — Use this TCL file to connect the generated block to the external peripherals on the hardware board. In addition to these connections, use this file to configure the HDL IP parameters.

The tool adds all the files and folders that you specify in the tool to the specified library location.

The tool adds the library folder to the MATLAB path. Save the current MATLAB path if you want to use the generated block in different MATLAB sessions.

You can now integrate the generated block with rest of your SoC Simulink model. Use the SoC Builder tool to simulate, build, and deploy the model on a hardware board.