System on Chip (SoC)

Combine processor software, programmable logic, memory, and peripherals into complete SoC designs

Create SoC, MCU, or application-specific SoC Simulink^® models of an application. Use preconfigured model templates or follow the SoC model guidelines. SoC Blockset™ model templates provide design patterns and implement best practices for creating an SoC model. The suggested workflow shows the process to combine processor software, user-specified programmable logic, shared memory systems, and on-chip peripherals to create an SoC model of an application. Use analysis functions and tools to estimate the resources that application uses. Compare different architectures to understand design tradeoffs in partitioning between processor software and programmable logic.

The blockset exports reference designs for SoCs, MCUs, ASICs, and FPGAs using Xilinx^®, Intel^®, and Texas Instruments^® design tools. Automatically generate hardware and software code, and then execute the application on an SoC device by using the SoC Builder tool. Code generation requires the HDL Coder™ product, Embedded Coder^® product, or both.

Apps

Embedded Linux Explorer

Connect to hardware, monitor resources, and control applications running embedded Linux (Since R2023a)

Tools

SoC Builder	Build, load, and execute SoC model on SoC, FPGA, and MCU boards
HDL IP Importer	Import HDL IP core into SoC model (Since R2023a)

Functions

`socModelAnalyzer`	Estimate number of operations in Simulink model (Since R2020a)
`socFunctionAnalyzer`	Estimate number of operations in MATLAB function (Since R2020a)
`socAlgorithmAnalyzerReport`	Open algorithm analysis report (Since R2020a)
`socExportReferenceDesign`	Export custom reference design for HDL Workflow Advisor (Since R2020a)
`socTaskSchedulability`	Determine whether set of tasks can be scheduled for specified core assignments (Since R2022b)
`socCreateModel`	Creates a skeleton SoC Blockset model for task set (Since R2022b)

Objects

socModelBuilder Build, load, and execute SoC model on SoC and FPGA boards (Since R2023a)

Model Settings

Hardware Implementation Pane

Topics

Processor, Programmable Logic, and Memory

SoC Blockset Model Structure
Top level structure of SoC model.
Use Template to Create SoC Model

Create SoC models using Simulink Project templates.
Create an SoC Project Application

Step by step instructions and guidelines to create an SoC Blockset project and models for an SoC application.
- STEP 1: Project and Top-Level Model
- STEP 2: Software and Task Management on Processor
- STEP 3: User Logic on FPGA
- STEP 4: Memory and Register Channel Connections
- STEP 5: Simulation and Analysis
SoC Generation Workflows

Choose between SoC Builder workflow or IP Core Generation workflow for deploying your design on an SoC device.
Generate SoC Software Model
Generate Simulink software models using the IP core generation workflow.
Custom Hardware Board Configuration
Develop an SoC application model with a custom board configuration.

Application-Specific SoCs

Use Template to Create SoC Model

Create SoC models using Simulink Project templates.
- RFSoC Template
- SDR Template
- HDMI Template
- Frame Buffer with HDMI Template

Architecture and Analysis

Using the Algorithm Analyzer Report
Navigate details of the report generated by the socModelAnalyzer or socFunctionAnalyzer function.

Troubleshooting

Build Error When FPGA or Processor Model Not Detected

Unsupported mode in when generating SoC design using SoC Builder.

Build Error for Rapid Accelerator Mode

Unsupported simulation mode in SoC Blockset models and projects.

Featured Examples

Streaming Data from Hardware to Software

A systematic approach to design the data-path between hardware logic (FPGA) and embedded processor using SoC Blockset™.

Open Script

Streaming Data from Software to Hardware

Design the data-path from an embedded processor to hardware logic (FPGA) using SoC Blockset™. Design and simulate the entire application comprising of FPGA and processor algorithms, memory interface, and task scheduling to meet the system requirements. Then, validate the design on hardware by generating code from the model and implementing it on a System-on-Chip (SoC) device.

Open Script

Triggering Software Tasks by FPGA Interrupts

Model an algorithm partitioned between hardware and software. The hardware IP is implemented in FPGA fabric, and triggers a software task implemented in the embedded processor. Design, simulate, and implement a complete design on SoC hardware.

Open Script

Use IP Core Generation Workflow with SoC Models

Use the IP core generation workflow to deploy an SoC model on an SoC board. In this example, you simulate, implement, and verify your design on hardware.

Open Live Script

Export Custom Reference Design

Export a custom reference design from an SoC model by using the Soc Blockset™ socExportReferenceDesign function. After creating the custom reference design, use the HDL Workflow Advisor tool from HDL Coder™ to integrate an IP core into the reference design.

Open Script

Estimate Number of Operators for MATLAB Algorithm

Estimate the number of arithmetic operators in an algorithm written in MATLAB®. Analyze a radix 2 FFT algorithm and generate reports showing operator usage.

Open Script

Compare FIR Filter Implementations Using socModelAnalyzer

Analyze and compare different implementations of a Simulink® algorithm based on the number of arithmetic operations. Use the SoC Blockset socModelAnalyzer function to generate reports that show the number of operators for different implementations of a FIR Filter using static and runtime execution.

Open Model

Systems Engineering Approach for SoC Applications

Design a sample signal detector application on a System on Chip (SoC) platform using a systems engineering approach. The workflow in this example maps the application functions onto the selected hardware architecture.

Open Live Script