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Use IP Core Generation Workflow with SoC Models

This example shows how to use the IP core generation workflow to deploy an SoC model on an SoC board. In this example, you simulate, implement, and verify your design on hardware.

Supported hardware platforms are:

  • Xilinx® Zynq® ZC706 evaluation kit

  • Xilinx Zynq UltraScale™+ RFSoC ZCU111 Evaluation Kit

  • Xilinx Zynq UltraScale+ RFSoC ZCU208 Evaluation Kit

  • Xilinx Zynq UltraScale+ RFSoC ZCU216 Evaluation Kit

If your SoC board is a Xilinx Zynq ZC706 evaluation kit, run install_rd_zc706 to install the ZC706 reference design.


This example shows how to use SoC Blockset™ and HDL Coder™ to design, simulate, and deploy a custom HDL IP core on an SoC board. Using SoC Blockset library blocks, you design and simulate your application, and then verify the behavior against external IO like DDR memory. Using SoC Blockset apps, you can then measure performance, evaluate scenarios, and optimize your algorithm to meet the constraint of a specific hardware platform. In this guided IP core workflow, you automatically generate a HDL IP, integrate the IP into a hardware reference design, and deploy the design on an SoC device. After deployment, you can interact with the design running on the board using MATLAB host interface scripts.

Model Structure

The model soc_image_rotation_refdes is a modified version of the soc_image_rotation model used in the Random Access of External Memory example.

soc_image_rotation_refdes.slx model

Memory: The Memory block models a random access memory region using an AXI4 Random Access Memory block:

  • The memory stores the input image and initializes the memory before the simulation starts. To see how model parameters and input data are initialized, open the preload simulation function soc_image_rotation_refdes_init.m.

  • The memory stores the rotated image and logs it at the end of the simulation. To see how input data and output data are plotted, open the stop simulation function soc_image_rotation_refdes_post.m.

FPGA: This subsystem instantiates the logic for AXI4 Manager interfaces and data rotation. For more details, see the Vertical Video Flipping Using External Memory example.

Control: The control block sends a start signal the image rotation algorithm.


Set the model to a supported SoC hardware board to simulate the proper memory timing. If your SoC board is not Xilinx Zynq UltraScale+ RFSoC ZCU111 evaluation kit, you must adjust the settings of the model:

  1. From the Simulink toolstrip, select the Hardware Settings in the System on Chip tab.

  2. In the Configuration Parameters window, select Hardware Implementation on the left pane and set Hardware board to match your board.

  3. In the Hardware board settings section, set Processing unit to FPGA.

  4. Expand Target hardware resources. Under Groups, click FPGA design (debug) and set Memory diagnostic level to Basic diagnostic signals.

Simulate the model and verify that the image rotates 180 degrees. You can compare the input and output images that are plotted at the end of simulation.

input image output image

To visualize the memory performance, after running the simulation, open the performance report:

  1. In the System On Chip toolstrip tab, click Performance Report.

  2. In the Performance Report window that opens, select PL Memory Controller in the Report Browser.

  3. Select Bandwidth in the Controls and select Master 1 and Master 2.

  4. Click Create Plot to display the bandwidth usage of the PL memory controller.

bandwidth usage of the PL memory controller


To generate a bitstream and deploy the design on a board, you must have these products:

  • HDL Coder™

  • SoC Blockset Support Package for Xilinx Devices

For more information about the Xilinx support package, see Xilinx Devices.

If your SoC board is a Xilinx Zynq ZC706 evaluation kit, run install_rd_zc706 to install the ZC706 reference design before continuing. You must close and reopen the model for the board to show in the Target Platform menu.

To implement the model on a supported SoC board, use the HDL Coder IP core generation workflow. To add the HDL Code tab to the Simulink toolstrip, open the Apps gallery and select HDL Coder.

Apps gallery

In the Configuration Parameters dialog box of the model, set the HDL workflow, target platform and reference design:

  1. In the left pane, select HDL Code Generation/Target.

  2. In Workflow, select IP Core Generation.

  3. In Target Platform, select the same board as the one selected in Hardware board under Hardware Implementation panel. (For the ZC706 board, select Xilinx Zynq ZC706 evaluation kit (SoCB)).

  4. In Reference Design, select an SoC Blockset reference design. For RFSoC boards, select Generic design with real DAC/ADC and real-time interfaces. For the ZC706 board, select Design with DDR3 Memory Access (SoCB).

  5. Set Target Frequency to 100 MHz.

  6. Click OK to save and close the dialog box.

Configuration Parameters dialog

Identify the IP core subsystem for code generation:

  1. Select the ImageRotation subsystem.

  2. In the HDL Code tab, pin the Code for selection.

HDL Code tab, Code for selection dialog

Provide the IP core interface mapping:

  1. In the HDL Code toolstrip tab, click Target Interface.

  2. In IP Core panel, select the Interface Mapping tab.

  3. In the Interface Mapping tab, click the refresh button.

  4. In the table, enter the IP Core port mapping for the ImageRotation subsystem.

  5. Click the validate button.

Interface Mapping table

Generate the HDL IP core and the FPGA bitstream files:

  1. In the HDL Code tab, click Build Bitstream.

  2. After the HDL IP core finishes generating, an external shell opens for FPGA synthesis. Wait for the synthesis to complete. The FPGA synthesis may take more than 30 minutes to complete.

For more information about the IP core generation workflow, see Getting Started with Targeting Xilinx Zynq Platform (HDL Coder).

Run on Hardware

Program the FPGA on the SoC board:

  1. In the HDL Code tab, click Deployment Settings.

  2. In the Deployment Settings window, provide the board connection information.

  3. In the HDL Code tab, click Program Target Device to program the board with the generated bitstream.

Generate the MATLAB host interface script and interact with the board:

  1. In the HDL Code tab, click Host Interface Script. Two MATLAB files are generated in your current folder, which enable you to communicate with the board from MATLAB:

  • gs_soc_image_rotation_refdes_setup.m contains the IP core interfaces information and setup.

  • gs_soc_image_rotation_refdes_interface.m is a template script on how to use these interfaces.

If your SoC board is Xilinx Zynq UltraScale+ RFSoC ZCU111 evaluation kit, you can use gs_soc_image_rotation_refdes_setup_zcu111.m and gs_soc_image_rotation_refdes_interface_zcu111.m.

2. If your board is not a ZCU111, modify the code in gs_soc_image_rotation_refdes_interface.m to load the image in memory, start the image rotation, and retrieve the rotated image from memory.

3. Run the modified gs_soc_image_rotation_refdes_interface.m script (or the gs_soc_image_rotation_refdes_interface_zcu111.m script) and verify the result.

For more information about the HDL Coder MATLAB host interface script, see Generate and Manage FPGA I/O Host Interface Scripts (HDL Coder).