SoC Blockset Model Structure

An SoC Blockset™ model consists of a top model that includes at least one of these reference models.

An FPGA reference model represents the FPGA part of an SoC device. The top model can include at most one FPGA reference model. For information on how to set up an FPGA reference model, see User Logic on FPGA.
A processor reference model represents the processor part of an SoC device. The top model can include one or more processor reference models. For information on how to set up a processor reference model, see Software and Task Management on Processor.

The processor and the FPGA subsystems communicate through a Memory Channel, Register Channel or Interrupt Channel block.

In addition to FPGA and processor reference models, the top model can include additional SoC Blockset blocks, such as the blocks listed here, for modeling interfaces and test bench components.

The following image shows an SoC Blockset model, with an FPGA reference model, a processor reference model, communicating over a memory channel.

Block diagram of top model. The top model includes an FPGA model, a processor model, a memory channel connected to a memory controller, and a register channel. The processor connects to a testbench unit with a scope to display simulation output.

For an example of an SoC Blockset model, see Streaming Data from Hardware to Software.

SoC Blockset provides project templates for common SoC use-cases. Use them as a starting point for your design.

SoC Blockset Model Structure

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