Configure Design Using SoC Model Creator

To open the SoC Model Creator tool, enter the socModelCreator command at the MATLAB^® command prompt. In the window that opens, select the reference design for which you want to create an SoC model. Select the type of model and customize the model by using the reference design parameters, predefined internal interfaces, external input/output (I/O) interfaces, and AXI registers.

Reference Design General

In the Reference Design General section, select the reference design board, reference design name, supported Vivado^® version, programming method, and target frequency.

Reference design board — Select the target hardware board for your reference design. By default, this parameter is set to Xilinx Zynq UltraScale+ RFSoC ZCU111 Evaluation Kit.
Reference design name — Select the reference design for which you want to create an SoC model. By default, this parameter is set to Real ADC/DAC Interface. Available options for this parameter vary as per the selected hardware board.
These are the reference design options for Xilinx^® Zynq^® UltraScale+™ RFSoC ZCU111 evaluation kit:
- Real ADC/DAC Interface — Select this option when your design receives and transmits real data.
- Real ADC/DAC Interface with PL-DDR4 — Select this option when your design receives and transmits real data, and uses DDR4 buffering. Selecting this option adds an AXI4 interface to your device under test (DUT) for connection to the DDR4 memory.
- IQ ADC/DAC Interface — Select this option when your design receives and transmits complex in-phase/quadrature (I/Q) data.
- IQ ADC/DAC Interface with PL-DDR4 — Select this option when your design receives and transmits complex I/Q data and uses DDR4 buffering. Selecting this option adds an AXI4 interface to your DUT for connection to the DDR4 memory.
These are the reference design options for Xilinx Versal^® AI Core Series VCK190 evaluation kit:
- Default system (default) — Select this option when your design requires the AXI4 register interface only.
- Default System with SoC Blockset Generic Design — Select this option when your design requires any or all of these interfaces: AXI4-Stream to software, software to AXI4-Stream, random access memory, interrupt, and/or AXI4 register. You can add any or all of these interfaces in a single design using this reference design.
Note
Other reference design options are also available, such as
- For RFSoC devices — Generic design with real DAC/ADC and real-time interfaces and Generic design with I/Q DAC/ADC and real-time interfaces
- For Versal devices — Default system with AXI4-Stream interface and Default system with External DDR4 Memory Access
Selecting these reference designs through SoC Model Creator is not a recommended workflow. Instead, to create a model for these reference designs, use the IP core generation workflow of the HDL Workflow Advisor.
Supported Vivado version — Select your Xilinx Vivado Design Suite from the list of supported Vivado versions.
Set the synthesis tool path to point to an installed Vivado Design Suite by entering this command at the MATLAB command prompt. When you execute this command, use your own Xilinx Vivado installation path.
```
hdlsetuptoolpath('ToolName','Xilinx Vivado','ToolPath', ...
 'C:\Xilinx\Vivado\2023.1\bin\vivado.bat');
```
Programming method — Set the method for programming the target hardware board to Ethernet or JTAG.
Target frequency (MHz) — Specify the target frequency to modify the clock module setting in the reference design. The reference design uses a clock signal with the specified frequency. Specify a target frequency value in the range [5, 500]. The default value is 50.
This parameter is available for Xilinx Zynq UltraScale+ MPSoC ZCU102 and Xilinx Versal AI Core Series VCK190 evaluation kits only.

Model Creation

In the Model Creation section, specify the name and select the type of your model.

Top model name — Specify the name of the top model (in SLX format) that you want to create. By default, this parameter is set to mySoCModel.slx.
Create models representing — Select the type of the SoC model that you want to create. The SoC model can be of these types.
- FPGA and processor (default) — Include an FPGA model, a processor model, and the register channel in your top model.
- FPGA and memory — Include an FPGA model and a memory system in your top model. The memory system can contain a memory controller and memory channels or a specialized memory block, such as AXI4 Random Access Memory, AXI4-Stream to Software, Software to AXI4-Stream, or AXI4 Video Frame Buffer.
- FPGA only — Include an FPGA model in your top model.
  Note
  For an FPGA only model, to generate a bitstream for your FPGA design and a compiled executable for your software, you must install the HDL Coder™ Support Package for Xilinx Zynq Platform and Embedded Coder^® Support Package for AMD SoC Devices.

Reference Design Parameters

The Reference Design Parameters section lists the parameters that are available with the selected reference design. Available options for these parameters vary as per the reference design that you select in the Reference Design General section.

These are the reference design parameters for RFSoC devices.

Select the AXI4-Stream DMA data width parameter as 32, 64, or 128 bits.
Specify the ADC sampling rate (MHz) and DAC sampling rate (MHz) parameters as scalars in a range that depends on the selected hardware board.
Select the ADC decimation mode (xN) parameter as the required decimation factor value and the DAC interpolation mode (xN) parameter as the required interpolation factor value.
Select the ADC samples per clock cycle and DAC samples per clock cycle parameters as the required number of ADC and DAC samples per clock cycle, respectively.
Select the ADC mixer type and DAC mixer type parameters as Bypassed, Fine, or Coarse. Available options for these parameters vary as per the selected reference design.
Specify the frequency of the numerically-controlled oscillator (NCO) mixer for an ADC and DAC channel by using the ADC/DAC NCO mixer LO (GHz) parameter.
Select the Enable multi-tile sync parameter as true to enable multi-tile synchronization (MTS). Enabling MTS has additional requirements. For more information on MTS mode, see Zynq UltraScale+ RFSoC RF Data Converter Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269) in the Xilinx documentation.
Do not change the values of the Tile clock output frequency (MHz) and DUT synthesis frequency (MHz) parameters. These values are prepopulated. The Tile clock output frequency (MHz) parameter shows the output clock frequency of the ADC and DAC tile, and the DUT synthesis frequency (MHz) parameter shows the synthesis frequency of the DUT.
Select the phase-locked loop (PLL) reference clock in MHz by using the PLL reference clock (MHz) parameter.
Select the Connect to AXI4-Master DDR4 MIG parameter as true to connect the model to DDR4 memory. Available options for this parameter vary as per the selected reference design.

The number of samples per clock cycle, or DMA data width, affect the data type of the signal lines to reflect the word length. For example, when you select 4 samples per clock cycle, the word length for the ADC or DAC I/O lines is 64 bits because each sample is 16 bits.

Internal Interfaces

In the Internal Interfaces section, you can customize the model with interfaces defined in the selected reference design. Internal interfaces vary depending on the reference design that you select in the Reference Design General section.

For RFSoC devices, you can customize the model with preconfigured DAC and ADC channels. The number of DAC and ADC tiles and the number of channels in each tile depend on the selected hardware board. For example, if you select the Xilinx Zynq UltraScale+ RFSoC ZCU111 evaluation kit, the DAC pane contains two tiles (Tile 0 and Tile 1), and each tile contains four DAC channels. The ADC pane contains four tiles (Tile 0, Tile 1, Tile 2, and Tile 3), and each tile contains two ADC channels. The tiles and DAC or ADC channels indicate the corresponding tiles and DAC or ADC interfaces on the selected hardware board.

External I/O Interfaces

In the External I/O Interfaces section, select the external I/O interfaces for your model from the available list of interfaces. These external I/O interfaces are board-specific and defined in the board definition file.

AXI Registers

In the AXI Registers section, you can add a new AXI register to your model by clicking New. Define the name, direction, data type, and dimension for the newly added register.

Name — Specify the name of the register.
Direction — Select the direction for the register as Write or Read.
Data type — Select the data type for the register as int8, uint8, int16, uint16, int32, uint32, boolean, fixdt(1,16,0), fixdt(1,16,2^0,0), or a custom data type.
Dimension — Specify the dimension of the register as a numeric scalar.

You can rearrange the register rows by clicking Move Up and Move Down. Select the row that you want to move up or move down, then click Move Up or Move Down. To delete register, select the register and click Delete.

Click Create. A created SoC model opens in a Simulink^® window. The SoC model maps the input and output ports to the various interfaces that are associated with the target board. You can add your algorithm to a subsystem in the created model for simulation, HDL code generation, and SoC deployment.

Note

After you create an SoC model for a specified reference design board, do not change the target hardware board. Even if you change the target board after you create an SoC model, the SoC Builder tool still generates HDL code for the target board for which you have created the model. To change the target hardware board, create a new SoC model for a required reference design board by using the SoC Model Creator tool.

You need not create a model again just to add an AXI register after you create the model. You can add the new AXI registers to the created model in Simulink and connect them to the Register Channel block in the top model.

Edit the created model to include the required algorithm. Navigate to the blocks marked FPGA Algorithm in the FPGA model or Processor Algorithm in the processor model. Replace these blocks with your own algorithm model. Then, simulate the system and use the SoC Builder tool to build software executables and an FPGA programming file from your model and program the target hardware board.

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