Vision
You can use SoC Blockset™ to model and simulate video processing algorithms such as histogram equalization. Simulate your algorithm with SoC components such as DDR memory, software tasks, and AXI interfaces. You can then take additional steps to deploy your design on an SoC device.
Featured Examples
Edge Detection and Image Overlay
Implement an edge detection and image overlay system with HDMI input and output.
Histogram Equalization Using Video Frame Buffer
Perform histogram equalization with HDMI input and output and using external memory for video frame buffering.
Vertical Video Flipping Using External Memory
Flip an incoming video stream vertically by using a random-access external memory interface.
Contrast Limited Adaptive Histogram Equalization with External Memory
Implement the contrast-limited adaptive histogram equalization (CLAHE) algorithm for FPGA, including an external memory interface.
YOLO v2 Vehicle Detector with Live Camera Input on Zynq-Based Hardware
Deploy a YOLO v2 vehicle detection algorithm to the FPGA and ARM® processor on an SoC device and process live HDMI video input.
(Vision HDL Toolbox)
Deploy and Verify YOLO v2 Vehicle Detector on FPGA
Deploy a you only look once (YOLO) v2 vehicle detector on FPGA and verify the end-to-end application using MATLAB.
(Vision HDL Toolbox)
Corner Detection with Zynq-Based Hardware and MIPI Sensor
Target a corner detection algorithm to a ZCU106 device with a MIPI® add-on card by using the SoC Blockset™ Support Package for AMD® FPGA and SoC Devices.
Low Light Enhancement with Zynq-Based Hardware
Target a low light enhancement algorithm to the Zynq® hardware using the SoC Blockset™ Support Package for AMD FPGA and SoC Devices.
MultiPixel-MultiComponent Streaming with Zynq-Based Hardware
Target multipixel multicomponent algorithm to the Zynq® hardware using the SoC Blockset™ Support Package for AMD® FPGA and SoC Devices.
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