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SM ST7C

Discrete-time or continuous-time synchronous machine ST7C static excitation system with automatic voltage regulator

Since R2023a

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Libraries:
Simscape / Electrical / Control / SM Control

Description

The SM ST7C block implements a synchronous-machine-type ST7C static excitation system model in conformance with IEEE Std 421.5-2016 [1].

Use this block to model the control and regulation of the field voltage of a synchronous machine.

Switch between continuous and discrete implementations of the block by using the Sample time (-1 for inherited) parameter. To configure the integrator for continuous time, set the Sample time (-1 for inherited) parameter to 0. To configure the integrator for discrete time, set the Sample time (-1 for inherited) parameter to a positive scalar. To inherit the sample time from an upstream block, set the Sample time (-1 for inherited) parameter to -1.

The SM ST7C block comprises three major components:

  • The Current Compensator component modifies the measured terminal voltage as a function of the terminal current.

  • The Voltage Measurement Transducer component simulates the dynamics of a terminal voltage transducer using a low-pass filter.

  • The Excitation Control Elements component compares the voltage transducer output with a terminal voltage reference to produce a voltage error value. The component then passes this value through a voltage regulator to produce the field voltage.

This diagram shows the structure of the ST7C excitation system model:

In the diagram:

  • VT and IT are the measured terminal voltage and current of the synchronous machine, respectively.

  • VC1 is the current-compensated terminal voltage.

  • VC is the filtered, current-compensated terminal voltage.

  • VREF is the reference terminal voltage.

  • VS is the power system stabilizer voltage.

  • EFD is the field voltage.

Current Compensator and Voltage Measurement Transducer

The block models the current compensator by using this equation:

VC1=VT+ITRC2+XC2,

where:

  • RC is the load compensation resistance.

  • XC is the load compensation reactance.

The block implements the voltage measurement transducer as a Low-Pass Filter block with the time constant TR. Refer to the documentation for the Low-Pass Filter block for information about the exact discrete and continuous implementations.

Excitation Control Elements

This diagram shows the structure of the excitation control elements:

In the diagram:

  • The Summation Point Logic subsystem models the summation point input location for the overexcitation limiter (OEL), underexcitation limiter (UEL), and stator current limiter (SCL) voltages. For more information about using limiters with this block, see Field Current Limiters.

  • There are two Take-over Logic subsystems. The subsystems model the take-over point input location for the OEL, UEL and SCL voltages. For more information about using limiters with this block, see Field Current Limiters.

  • A Lead-Lag block in series introduces a derivative function and transforms the regulator in a PID. This is typically used only with brushless excitation systems.

  • KL and KH model a high-bandwidth regulator inner loop that regulates the generator exciting current.

Field Current Limiters

You can use different types of field current limiter to modify the output of the voltage regulator under unsafe operating conditions:

  • Use an overexcitation limiter to prevent overheating of the field winding due to excessive field current demand.

  • Use an underexcitation limiter to boost field excitation when it is too low, which risks desynchronization.

  • Use a stator current limiter to prevent overheating of the stator windings due to excessive current.

Attach the output of any of these limiters at one of these points:

  • Summation point — Use the limiter as part of the automatic voltage regulator (AVR) feedback loop.

  • Take-over point — Override the usual behavior of the AVR.

If you are using the stator current limiter at the summation point, use the input VSCLsum. If you are using the stator current limiter at the take-over point, use the overexcitation input VSCLoel, and the underexcitation input VSCLuel.

Ports

Input

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Voltage regulator reference set point, in per-unit representation, specified as a scalar.

Data Types: single | double

Input from the power system stabilizer, in per-unit representation, specified as a scalar.

Data Types: single | double

Terminal voltage magnitude, in per-unit representation, specified as a scalar.

Data Types: single | double

Terminal current magnitude, in per-unit representation, specified as a scalar.

Data Types: single | double

Input from the overexcitation limiter, in per-unit representation, specified as a scalar.

Dependencies

  • To ignore the input from the overexcitation limiter, set Alternate OEL input locations (V_OEL) to Unused.

  • To use the input from the overexcitation limiter at the summation point, set Alternate OEL input locations (V_OEL) to Summation point at voltage reference.

  • To use the input from the overexcitation limiter at the Take-over Logic subsystem, set Alternate OEL input locations (V_OEL) to Take-over at voltage error.

  • To use the input from the overexcitation limiter at the Take-over Logic1 subsystem, set Alternate OEL input locations (V_OEL) to Take-over at voltage regulator output.

Data Types: single | double

Input from the underexcitation limiter, in per-unit representation, specified as a scalar.

Dependencies

  • To ignore the input from the underexcitation limiter, set Alternate UEL input locations (V_UEL) to Unused.

  • To use the input from the underexcitation limiter at the summation point, set Alternate UEL input locations (V_UEL) to Summation point at voltage reference.

  • To use the input from the underexcitation limiter at the Take-over Logic subsystem, set Alternate UEL input locations (V_UEL) to Take-over at voltage error.

  • To use the input from the underexcitation limiter at the Take-over Logic1 subsystem, set Alternate UEL input locations (V_UEL) to Take-over at voltage regulator output.

Data Types: single | double

Input from the stator current limiter when using the summation point, in per-unit representation, specified as a scalar.

Dependencies

  • To ignore the input from the stator current limiter, set Alternate SCL input locations (V_SCL) to Unused.

  • To use the input from the stator current limiter at the summation point, set Alternate SCL input locations (V_SCL) to Summation point at voltage reference.

Data Types: single | double

Input from the stator current limiter to prevent field overexcitation when using the take-over point, in per-unit representation, specified as a scalar.

Dependencies

  • To ignore the input from the stator current limiter, set Alternate SCL input locations (V_SCL) to Unused.

  • To use the input from the stator current limiter at the Take-over Logic subsystem, set Alternate SCL input locations (V_SCL) to Take-over at voltage reference.

  • To use the input from the stator current limiter at the Take-over Logic1 subsystem, set Alternate SCL input locations (V_SCL) to Take-over at voltage regulator output.

Data Types: single | double

Input from the stator current limiter to prevent field underexcitation when using the take-over point, in per-unit representation, specified as a scalar.

Dependencies

  • To ignore the input from the stator current limiter, set Alternate SCL input locations (V_SCL) to Unused.

  • To use the input from the stator current limiter at the Take-over Logic subsystem, set Alternate SCL input locations (V_SCL) to Take-over at voltage error.

  • To use the input from the stator current limiter at the Take-over Logic1 subsystem, set Alternate SCL input locations (V_SCL) to Take-over at voltage regulator output.

Data Types: single | double

Output

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Per-unit field voltage to apply to the field circuit of the synchronous machine, returned as a scalar.

Data Types: single | double

Parameters

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General

Initial per-unit voltage to apply to the field circuit of the synchronous machine.

Time between consecutive block executions. During execution, the block produces outputs and, if appropriate, updates its internal state. For more information, see What Is Sample Time? and Specify Sample Time.

For inherited discrete-time operation, set this parameter to -1. For discrete-time operation, set this parameter to a positive integer. For continuous-time operation, set this parameter to 0.

If this block is in a masked subsystem or a variant subsystem that supports switching between continuous operation and discrete operation, promote this parameter to ensure correct switching between the continuous and discrete implementations of the block. For more information, see Promote Block Parameters on a Mask.

Pre-Control

Resistance used in the current compensation system. Set this parameter and Reactance component of load compensation, X_C (pu) to 0 to disable current compensation.

Reactance used in the current compensation system. Set this parameter and Resistive component of load compensation, R_C (pu) to 0 to disable current compensation.

Equivalent time constant for the voltage transducer filtering.

Control

Equivalent time constant for the voltage filtering.

Equivalent lag time constant of the voltage regulator, in seconds.

Maximum per-unit voltage reference of the voltage regulator.

Minimum per-unit voltage reference of the voltage regulator.

Per-unit gain of the voltage regulator.

Equivalent lag time constant of the voltage regulator. Set this parameter to 0 when the additional lag dynamics are negligible.

Equivalent lead time constant of the voltage regulator. Set this parameter to 0 when the additional lead dynamics are negligible.

Equivalent time constant in the thyristor bridge firing control.

Maximum per-unit output of the regulator.

Minimum per-unit output of the regulator.

Overexcitation limiter input location, specified as one of these options:

  • Summation point at voltage reference — V_OEL is an input of the Summation Point Logic subsystem.

  • Take-over at voltage reference — V_OEL is an input of the Take-over Logic subsystem.

  • Take-over at voltage regulator output — V_OEL is an input of the Take-over Logic 1 subsystem.

Underexcitation limiter input location, specified as one of these options:

  • Summation point at voltage reference — V_UEL is an input of the Summation Point Logic subsystem.

  • Take-over at voltage reference — V_UEL is an input of the Take-over Logic subsystem.

  • Take-over at voltage regulator output — V_UEL is an input of the Take-over Logic 1 subsystem.

Stator current limiter input location. specified as one of these options:

  • Summation point — Use the V_SCLsum input port.

  • Any of the Take-over options — Use the V_SCLoel and V_SCLuel input ports.

Exciter

Minimum per-unit gain of the exciter.

Maximum per-unit gain of the exciter.

Per-unit feedback gain of the PI regulator.

Feedback time constant of the Pi regulator, in seconds.

References

[1] IEEE Std 421.5-2016 (Revision of IEEE Std 421.5-2005). "IEEE Recommended Practice for Excitation System Models for Power System Stability Studies." Piscataway, NJ: IEEE, 2016.

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

Version History

Introduced in R2023a

See Also

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