Generate RFSoC Design
This tutorial outlines the steps to build hardware and software executables for your SoC model and execute your application. After you create an SoC model using the SoC Model Creator tool, use the SoC Builder tool to generate an HDL IP, build a bitstream, and program a Xilinx® Zynq® UltraScale+™ RFSoC ZCU111 board or Xilinx Zynq UltraScale+ RFSoC ZCU216 board.
After you create an SoC model for a specified reference design board, do not change the target hardware board. Even if you change the target board after you create an SoC model, the SoC Builder tool still generates HDL code for the target board for which you have created the model. To change the target hardware board, create a new SoC model for a required reference design board by using the SoC Model Creator tool.
Step 1: Set Up FPGA Design Software Tools
Set up your system environment for accessing Xilinx tools from MATLAB® by using the
hdlsetuptoolpath function. This
function adds the specified installation folder to the MATLAB search path. This example assumes that Xilinx
Vivado® is installed in the folder
This workflow supports Xilinx Vivado version 2020.2 only.
hdlsetuptoolpath('ToolName','Xilinx Vivado', ... 'ToolPath','C:\Xilinx\Vivado\2020.2\bin\vivado.bat')
Step 2: Start SoC Builder
Start the SoC Builder tool. In the Simulink® toolstrip, on the System on Chip tab, click Configure, Build & Deploy.
Step 3: Prepare Model for Generation
Prepare your model by selecting a starting point for the build process and then reviewing the model information.
If SoC Builder detects no support package, SoC Builder prompts you to install the required support package before going to the Setup section.
Select the starting point for the build process. If you are building a model that you have not built before, select Build using fixed reference design. If you have previously completed the build process and saved the binaries in a folder, select Load existing binaries.
If you do not want to build your model using a fixed reference design and want to switch to the regular SoC Builder tool, click the link provided in the About Your Selection section. Close and then relaunch the SoC Builder tool. If you want to switch back to the fixed reference design workflow, enter this command at the MATLAB command prompt, and then relaunch the SoC Builder tool.
For more information about various SoC generation workflows, see SoC Generation Workflows.
SoC Builder parses the model and displays the top model, the FPGA model, and the processor model (if one exists). Review this information for accuracy. If any of the information is incorrect, revise the model, save the model, and then restart the SoC Builder tool.
The next page of SoC Builder provides information about the task map of the model. To open the Task Mapping tool, click View/Edit. View and edit the map of tasks in the SoC model to interrupt service routines (ISRs) on the hardware board.
This task map step of SoC Builder is available only if you have a processor model in your top model.
The next page of SoC Builder provides information about the memory map of the model. To open the Memory Mapper tool, click View/Edit. Review the base addresses and offsets. Edit the offsets if needed. In this workflow, the Memory Mapper tool shows the device under test (DUT) and its registers.
Step 4: Select Project Folder
Specify a path to a project folder by entering the path in the Project Folder box or by browsing to a folder location. SoC Builder places all of the generated files, including reports, executables, and the bitstream, in this specified folder.
If you selected Load existing binaries as the starting point for the build process, specify the project folder location of the previous binaries and reports.
Step 5: Select Build Action
In the Select Build Action section, select one of these options:
Build, load, and run – Select this option to generate HDL and C code and to build software executables and an FPGA programming file from your model. After building, SoC Builder loads the generated code to the RFSoC board and executes the application.
Build only – Select this option to generate HDL and C code and to build software executables and an FPGA programming file from your model. SoC Builder saves the generated binaries in a folder, and you can continue execution later.
Build and load for external mode – Select this option to build the design and run it in external mode. External mode enables you to tune parameters on the FPGA without having to rebuild the FPGA design. It also enables logging data from the FPGA and displaying it on the host. For more information about external mode, see External Mode Simulations for Parameter Tuning and Signal Monitoring (Simulink Coder).
Step 6: Validate Model
Check the model against the selected board by clicking Validate.
Step 7: Build Model
To generate a bitstream for your FPGA design and a compiled executable for your software, click Build.
Clicking Build opens an external shell and runs third-party tools for synthesis and implementation of the design. The generation time depends on the complexity of your model and your host computer.
Step 8: Connect Hardware
Review the IPv4 address, SSH port number, and login credentials. Edit any of these values if needed. This step is critical if you have more than one board connected to the host computer so that SoC Builder can identify the correct port connection. Verify that the displayed IP address matches the IP address for the board you intend to use.
Verify that the board is connected to the host with an Ethernet cable, and then click Test Connection to test the physical connection to the board.
Step 9: Load and Run
If your top model includes an FPGA model, but no processor model, the Load and Run button is labeled Load instead.
Verify that your board is connected to the host computer via an Ethernet cable. Click Load and Run. This action loads the generated bitstream to the FPGA, programs the processor, and runs the application.
If you selected Build and load for external mode in step 5, this action loads the bitstream to the FPGA and opens the model in external mode. You can now choose signals for logging and monitoring or change tunable parameters. To run the instrumented application on hardware, in the Run on Hardware section on the System on Chip tab, click Monitor and Tune. If you previously built and loaded your design to an FPGA, click Connect. This action connects your instrumented Simulink model to the FPGA model.
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