How do I input a large Excel data set when using HDL coder?

2 次查看（过去 30 天）
Christiaan
Christiaan 2014-1-7
评论： Tim McBrayer 2014-1-8
Hi,
I am making an easy trading algorithm which should run on an fpga. I want to use massive datasets but get an error message in the HDL verify part of the workflow which says my data set is too large. (this dataset only has 879 entries)
Also, which of the generated files do I use to run my Fpga in the loop? Can I use the testbench_fil file?

请先登录，再回答此问题。

回答（1 个）

Tim McBrayer
Tim McBrayer 2014-1-7
You need to make sure your dataset is being read by your testbench and then fed to your design in a hardware-friendly fashion. When using FIL, the full dataset needs to reside in Simulink and be passed to your design element by element. This is a requirement due to the limited number of pins on an FPGA. For example 879 data values, if they were 32-bit integers, would require over 28000 pins to pass at once onto an FPGA.
For a simple discussion of testbenches for HDL Coder, see this <http://www.mathworks.com/matlabcentral/answers/109999-how-to-make-a-test-bench-file-for-a-matlab-m-file answer>.
  2 个评论
Christiaan
Christiaan 2014-1-8
Thanks! I am still having problems feeding the data to the design in a hardware friendly manner. What would be the best way to read it in if the data looks like :
Close = [111.090000000000;111.850000000000;111.890000000000;112.200000000000;....] with lots of elements.
Thanks in advance, Christiaan
Tim McBrayer
Tim McBrayer 2014-1-8
If the data is just a vector, you'd want to pass it into the design one element at a time. You will need to consider how much data you need to have on hand at any instant inside your design. You can use Block RAMs to store reasonable amounts of data on an FPGA. But, as with all FPGA resources, there are limits.
You will also need to choose a data type that minimizes the number of bits while also minimizing the error when converting from floating to fixed point. For example, the data above shows precision down to 0.01. This means you should be looking to use at least 7 fractional bits. This makes your minimum step size 1/128. More fractional bits will minimize your conversion error, while increasing the size of your hardware.

请先登录，再进行评论。

类别

在 Help Center 和 File Exchange 中查找有关 FPGA, ASIC, and SoC Development 的更多信息

标签

产品

Community Treasure Hunt

Find the treasures in MATLAB Central and discover how the community can help you!

Start Hunting!

Translated by