hdl coder synchronism problem

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Marco
Marco 2014-4-30
评论： Marco 2014-5-2
Hi all, I have a problem related to synchronism of the paths of the simulink model shown in the attached figure after the simulink-vhdl conversion. As you can see from figure there is a path without any delay so after vhdl conversion this path is translated in a pure combinatorial logic while the paths with the delay are translated in a process with clock and reset in the sensitivity list. This has 2 main effects: - the overall output is asynchronous so it changes not only during the positive edge of the clock (as I want) - during the reset phase the output doesn't reset since no process with a reset is present in the path without delay. I tried to insert a zero-order hold at the input to synchronise the paths but this trick doesn't work. Any idea about my issue?? Thanks

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Tim McBrayer
Tim McBrayer 2014-5-1
Can you register your inputs our outputs (or both)? HDL Coder supports this via its subsystem pipelining capability; this can be implemented without modifying the Simulink diagram or changing the Simulink simulation behavior. You can access the HDL-specific settings by right-clicking on the subsystem and choosing HDL Code>HDL Block Properties.
An alternative solution, of course, is to add any necessary additional delays directly to the Simulink model.

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