Error in FIL simulation at the second time it's running

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Kyoji Marumoto 2021-9-14

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编辑： Kyoji Marumoto 2021-9-21

Once FIL simulation running, I encounted terminate simulation with "MEX S-function 'filsfun',(mdlOutput) error at time 0.0"

at the second time it's running. It even occured without changing Simulink model.

Also diagnosis viewer showed "Warning: A FIL protocol error has occurred: Expected a status packet." before stop simulation.

I am working that with MATLAB R2019a.

After Error with stop simulation the FIL simulation works with downloading FPGA data file to FPGA board.

But also the error occured at the second time it's runnning.

Is there any way to recover/re-establish the Ethernet FIL protocol communication setting?

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Answer 1

Marc Erickson 2021-9-14

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Double check that the bitstream you are using was created with the same version of Simulink as you are running your model with. I think you found one workaround: re-download the bitstream. Another potential workaround is to close and re-open the model, but that is less likely to work. This is not expected behavior, so if you want us to take a look, you can file a support request and we'll see what we find. If for an commercial off-the-shelf board, it is best if you can supply the bitstream and FIL block.

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Kyoji Marumoto 2021-9-14

编辑：Kyoji Marumoto 2021-9-21

Hi Marc, Thank you for your suggestion.

Regarding the differencies MATLAB version between FilWizard, generating sof, and Executing Simulink FIL simulation, I worked on both process with same version R2019a.

>>Another potential workaround is to close and re-open the model, but that is less likely to work.

Yes I couldn't solve the problem even many time reopen the FIL model and try FIL simulation twice or more already.

>>This is not expected behavior, so if you want us to take a look, you can file a support request and we'll see what we find.

Sorry since the model is our commercial product model, I can't file to a support request.

>>If for an commercial off-the-shelf board, it is best if you can supply the bitstream and FIL block.

I used off-the-shelf board DE2-115(Intel) and I can file Stream and FIL block (modified terminal name for confidencial issue). I already request a customor support in Japan. Is it possible to request US customer support directory and where can i request to?

And I'm now proceeding FPGA project file modification to modify to met the all clock slack. If you are familier with internal Ethernet controller design which clock,ETH_RXCLK,generated PLL clocks and virtual clock does related in the FIL communication protocol error after FIL running once.

Thank you.

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