Hi Gran,
Have you checked out our troubleshooting page for FIL (https://www.mathworks.com/help/hdlverifier/ug/troubleshooting-fil.html)? Furthermore, please ensure your host NIC is configured correctly. This PID FIL demo goes through the steps for configuring the host NIC (https://www.mathworks.com/help/hdlverifier/ug/verify-hdl-implementation-of-pid-controller-using-fpga-in-the-loop.html). If you are using your own design, please try this PID FIL demo first or use use our validation tool (https://www.mathworks.com/help/hdlverifier/ug/add-custom-fpga-board-for-fpga-in-the-loop-simulation.html#btmi8fy-42). If you are using the validation UI tool please ensure you are trying this out in a clean directory so the generated files don't get clobbered with existing files in that working directory. We need to make sure we can ping the board successfully first.
If the issue persists and you need further assistance, please submit a technical support ticket.
Regards,
