Can I use HDL Verifier cosimulation blocks in a Simulink model with continuous states?

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David 2014-10-8

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评论： Dan Massie 2016-1-28

In the HDL co-simulation tutorial provided by Mathworks (page 4-63 of the HDL Verifier User's Guide, R2014A), I read the sentence: "Configure the Simulink solver options for a fixed-step, discrete simulation; this is required for cosimulation operation." For the simple model being described in the tutorial, using the fixed-step solver makes sense. But this sentence makes it sound like the fixed-step solver must be used for all models which include co-simulation blocks. This would mean that co-simulation cannot be applied in models which have blocks with continuous states outside the HDL block. Is this correct? Or is this just a poorly-worded sentence in the tutorial?

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Dan Massie 2016-1-28

Did you ever get an answer to this question? Can you have continuous states outside of the HDL block? Thanks.

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Answer 1

Sandip Kumar 2014-10-9

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https://ww2.mathworks.cn/matlabcentral/answers/157889-can-i-use-hdl-verifier-cosimulation-blocks-in-a-simulink-model-with-continuous-states#answer_154573

During HDL co-simulation using HDL Verifier, the generated HDL code is being tested. The HDL code generation step requires Fixed-step and discrete (recommended) as options as listed here:

http://www.mathworks.com/help/releases/R2014b/hdlcoder/ug/hdl-workflow-advisor-tasks.html#bs8lmzh-39

And more information about them is covered in the 'hdlSetup' function documentation:

http://www.mathworks.com/help/hdlcoder/ref/hdlsetup.html

Also as mentioned :

Solver: Discrete (no continuous states). Other fixed-step solvers could be selected, but this option is usually the best one for simulating discrete systems.

As it says, it is recommended, which means if needed you can always select another solver option under 'Fixed-Step'.

Thanks, Sandip, MathWorks

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David 2014-10-9

Thank you for your response. But my question is a little different, because I am not using HDL Coder to generate the HDL code. Instead, I have written Verilog code manually, and then want to use HDL Verifier alone to verify that the code will work as expected as part of a model that also contains continuous states. The HDL Verifier cosimulation block itself will operate on port sample times which are uniformly spaced, but other portions of the model require the use of a continuous time solver. But based on the line from the documentation that I quoted in my original posting, I still wonder if this approach will generate an error.

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