HDL FFT Optimized. Valid Out always high

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Lennart
Lennart 2014-10-13
回答： Alireza 2014-11-19
Hi everybody,
I'm currently using the FFT HDL Optimized Block in my project and I wonder why my Valid Out is ALWAYS high. Even if I stop to feed the FFT with new values it remains high. The output is nothing usefull and for sure not the spectrum of the input data. Does anyone know that problem?
What I did: I generated the VHDL Code from a simulink Modell which ONLY contained the FFT Block and In- and Outputs (Data_In, Valid_In, Data_Out, Valid_Out). Is it useful that I put my sourcecode here? I guess it would be rather confusing so I leave it out for now. Please let me know if it would help so I can add it later on. In the Simulink simulation I had the same problem. The FFT continuously got input values. It continuously outputted the correct spectrum again again and again without pulling valid_out back to low at any moment. Is that how it is supposed to work? According to the timing graphs in the documentation it is not is it?
Thank you for your time and help!

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Alireza
Alireza 2014-11-11
Hi Lennart,
The HDL is verified and matches Simulink behavior. One thing that you can do to verify the result is to generate HDL and HDL test bench, and run the test bench in ModelSim (or any HDL Simulator). Note that the FFT output is in bit reversed order in 14a release. In 14b you can choose between bit reversed and natural order output.

更多回答（7 个）

Alireza
Alireza 2014-10-14
This is a bug in our implementation - we are looking into a patch for the issue.
Lennart
Lennart 2014-10-15
Wow ... good to know. What exactly is the bug about? Is it just the valid_out signal or is it the entire FFT? In the Simulink simulation the FFT outputs the correct spectrum. But I can't get it to work in my VHDL project. Should it output the correct spectrum or does the bug affect the results as well?
Thanks for your reply! You just safed me a lot of time!
Alireza
Alireza 2014-10-15
If you keep validIn high, the result is correct. Even in case the valid in is toggling, the HDL sends out the FFT of the input, mixed with some invalid data. But since valid out is high all the time, you don't know which output sample is correct and which one is not.
Lennart
Lennart 2014-10-15
Alright. Guess I will ground the project then. Probably would be quite helpful if this would have been said in the documentation so that other people don't have to waist a lot of time on this ...
Lennart
Lennart 2014-11-4
Hi Alireza,
I hope you're still reading this thread. I tried to keep valid_in high and feed the FFT with a sinusoid signal but the result rather looks like noise than a sinusoid with a few unvalid samples. Has your statement ever been verified in HDL oder only in Simulink? In my Simulink Model it works fine according to your description. In VHDL it doesn't.
Lennart
Lennart 2014-11-16
Hi Alireza,
I already did create a testbench and took care about the bitreverse order of the output. I simulated it with Xilinx' ISim but the output is anything but correct. After the first approx 200 samples (of a N=128 FFT) the output changes and than starts to repeat itselfe with some output which definitelly is not right either. I figured out that we got the R2014b Version as well now. Is that valid out bug fixed in that version?
Alireza
Alireza 2014-11-19
Hi Lennart,
Here is the website that you can download the patch for 14a and 14b. Please read the release notes because the patch will upgrade the FFT to the latest version and you get more features. http://www.mathworks.com/support/bugreports/1090560
Please let me know how it goes and if the patch fixes your problem.

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