sending complex signal through AXI-lite

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Hassan Khan
Hassan Khan 2022-2-7
评论： JT Ferrara 2022-2-9
hello,
i am using zynq706. i want to send a complex signal through AXI4-lite into FPGA. i have made the bit file of it. but when i run the interface model, AXI4-lite only 1 sample each time and not a whole frame . so is there any method to send a whole frame instead of 1 sample of that frame.
THANKS

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回答（1 个）

JT Ferrara
JT Ferrara 2022-2-7
Hi Hassan,
HDL Coder does not currently support sending complex data over AXI4-Lite directly. As a workaround, you can split the complex signal into real and imaginary parts and concatenate them as a vector. You can then map this vector to AXI4-Lite and reconstruct the complex signal inside of the DUT.
Best,
JT
  2 个评论
Hassan Khan
Hassan Khan 2022-2-8
Thanks for the response.
i have already tried the above mention method, but it gives only 1 sample each time when the simulation is running and not a whole frame. i have generated HDL code of this design. but when i start the simulation, AX_4 lite only passes 1 sample of the frame and not a whole frame. i want to multiply the whole frame with incoming data receiving from AD9361 receiver.
THANKS
JT Ferrara
JT Ferrara 2022-2-9
Hi Hassan,
Can you please share you model so that I may better understand your design?
Ports mapped to AXI4-Lite will become registers in the generated code. If you want to send a frame data, it may be better to use the AXI4-Stream interface. You can learn more about modeling for the AXI4-Stream interface here:
https://www.mathworks.com/help/hdlcoder/ug/model-design-for-axi4-stream-interface-generation.html
Note that the AXI4-Stream interface supports complex ports.

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