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JT Ferrara

Last seen: 8 days 前 |  自 2018 起处于活动状态

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  • Knowledgeable Level 3
  • 3 Month Streak
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已回答
Multiple IOSTANDARDs for a single HDL coder interface
You can define IOPadConstraint in one of two ways: The same IOPadConstraint for all pins in the interface. For this case, use a...

4 months 前 | 1

| 已接受

已回答
sending complex signal through AXI-lite
Hi Hassan, HDL Coder does not currently support sending complex data over AXI4-Lite directly. As a workaround, you can split th...

2 years 前 | 0

已回答
Multiple outputs from HDL block in simulink
Hi Muhammad, HDL Coder supports generating an IP core with multiple AXI4-Stream channels. There are two ways to generate such a...

2 years 前 | 1

| 已接受

已回答
Control the gain variable inside the generated IP block
Hi Anoop, This can be accomplished in two different ways: 1) Define a tunable parameter for your gain block, then map this tun...

2 years 前 | 0

| 已接受

已回答
How to deploy the interface model to SD card of Xilinx Zynq ZCU102 kit so that it will run everytime I power up my hardware ?
Please check out this MATLAB Answers post on this topic: https://www.mathworks.com/matlabcentral/answers/474175-how-do-i-deploy...

2 years 前 | 0

| 已接受

已回答
No system or file called 'axiinterfacelib' found
You can also bypass this error message by unchecking the box for "Generate Software Interface Model" in Task 4.2.

2 years 前 | 3

已回答
Processor and FPGA Synchronization in Coprocessing Mode
Hi Joaquin, When you select "Coprocessing -- Blocking mode", HDL Coder generates two synchronization registers in your IP core ...

3 years 前 | 0

| 已接受

已回答
How do I assign external ports in the Workflow Advisor for the ADRV9361-Z7035 evaluation board mounted on the ADRV1-CRR-BOB
Hi Christian, Based on your description, it sounds like you are correctly specifying the external ports. Can you please check t...

3 years 前 | 0

| 已接受

已回答
When mapping Input/Output data vector port to AXI4-Stream, Is there any way to enter 32-bit width data while using IP Core Generation workflow?
Hi Omer, There are two modeling styles you can use when mapping to an AXI4-Stream interface: (Sample-based modeling) Model the...

3 years 前 | 0

已回答
HDL-Coder AXI-Vector Strobe Register validation model
Hi Tobias, The validation model generated by HDL Coder only compares the original DUT model against changes due to area and tim...

3 years 前 | 1

| 已接受

已回答
mw_setbook command not found
The "mw_setboot" command is part of the MathWorks Linux image that comes with one of the following Embedded Coder hardware suppo...

4 years 前 | 0

已回答
Rate transitions and HDL generation port requirement
Hi Michael, The error you are encountering is due to the input ports (which are connected to the AXI4-Stream Slave interface) r...

4 years 前 | 0

| 已接受

已回答
Required Linux image / utilitys for IntelSoC custom boards
Hi Dominique, The default programming method over the HPS assumes you are using the Mathworks Embedded Coder Linux image. Since...

4 years 前 | 1

| 已接受

已回答
How do I specify an FPGA output as interrupt source for the ARM processor in Zedboard
Hi Klaus, FPGA generated interrupts are not currently supported out-of-the-box, but can be accomplished by connecting a DUT por...

5 years 前 | 2

| 已接受

已回答
Is there a compatibility for the Dalsa Xtium-cl mx 4 frame grabber card under development
Hi James, The R2018b release of MATLAB is now available, and with it Teledyne DALSA Sapera support now uses driver version 8....

5 years 前 | 1

已回答
Can I use The following Bluetooth adapter to connect the mambo mini drone to matlab?
Hi Luis, Compatible Bluetooth adapters for the PARROT Mambo must use the CSR Bluetooth stack, which your device does. The dev...

5 years 前 | 0

已回答
How to create, connect and use a ni visa device in Matlab?
Hi Pirmin, The value for "rsrcname" is the resource name for the VISA instrument. The format for resource name depends on the...

5 years 前 | 1

| 已接受