Error using () Data type mismatch at signal 'c_out'.This port expects a Logic data type of size 1

5 次查看（过去 30 天）
Deeksha R
Deeksha R 2022-4-21
回答： Marc Erickson 2022-11-14
This is my full adder code
module fulladder ( input [3:0] a,
input [3:0] b,
input c_in,
output c_out,
output [3:0] sum);
assign {c_out, sum} = a + b + c_in;
endmodule
Im trying to run cosimWizard from matlab.
In output port details pane, i selected Double data type for c_out, and fixedpoint signed datatype for sum.
but im getting the below error
Error using ()
Data type mismatch at signal 'c_out'.This
port expects a Logic data type of size 1
what should i assign output datatypes for c_out and sum?

请先登录，再回答此问题。

回答（1 个）

Marc Erickson
Marc Erickson 2022-11-14
The module port declarations are (implicitly) declaring c_out and sum as net types of wire and data type of logic (1 bit and 4 bits respectively). The cosimulation interface will expect Simulink or MATLAB data types that match the bit widths in the Verilog.
I do not understand what the module implementation is trying to do, but you should reexamine that.
To use 'double' in MATLAB/Simulink: in Verilog, use a 64bit logic type and the $bitstoreal / $realtobits system functions.

类别

在 Help Center 和 File Exchange 中查找有关 Simulink Cosimulation 的更多信息

标签

产品


版本

R2022a

Community Treasure Hunt

Find the treasures in MATLAB Central and discover how the community can help you!

Start Hunting!

Translated by