Code Generation for d flipflop
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Hi team,
i have D Flipflop in my simulink model ,when i am trying to generate vhdl code from the model i am getting the error like " Input port 'D' must not have 'Latch input by delaying outside signal' selected for HDL code generation".Please suggest me how i can proceed further by resolving this error.
Best Regards,
Rajini
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Bharath Venkataraman
2022-4-25
0 个投票
Do you really need to model the D Flip Flop (especially the clock)? If not, I suggest using the Delay block (with enable if you need it). The generated HDL will have a clock port you can drive in the hardware.
7 个评论
Rajini Gajula
2022-4-28
Bharath Venkataraman
2022-4-28
The Delay block has options to add enable, reset inputs ports and the data input, which I think should meet your needs.
If all you are trying to model is a delay by a clock and the ability to do synchronous reset, and enable, the delay block will work for you.
You can add in the state control block (synchronous mode) to model the HDL behavior for enable & reset.
Rajini Gajula
2022-4-29
Bharath Venkataraman
2022-4-29
Here is a simple model that shows how the delay block works.
Rajini Gajula
2022-5-2
Bharath Venkataraman
2022-5-2
The model for 18b is attached - hope this works.
Rajini Gajula
2022-5-4
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