Code Generation for d flipflop

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Rajini Gajula
Rajini Gajula 2022-4-22
评论： Rajini Gajula 2022-5-4
Hi team,
i have D Flipflop in my simulink model ,when i am trying to generate vhdl code from the model i am getting the error like " Input port 'D' must not have 'Latch input by delaying outside signal' selected for HDL code generation".Please suggest me how i can proceed further by resolving this error.
Best Regards,
Rajini

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采纳的回答

Bharath Venkataraman
Do you really need to model the D Flip Flop (especially the clock)? If not, I suggest using the Delay block (with enable if you need it). The generated HDL will have a clock port you can drive in the hardware.
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Rajini Gajula
Rajini Gajula 2022-5-4
Thank you so much sir,it is working.

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