The HDL Coder Workflow Advisor can backannotate either the pre- or post- Place and Route timing information from supported synthesis tools onto the Simulink model. This takes into account not only the logic delay but also the routing delay of the FPGA.
You should use the "Generic ASIC/FPGA" target workflow, selected in step 1.1 in the HDL Workflow Advisor. Once you have selected a synthesis tool and a specific target FPGA part, examine the choices shown in step 4.3 for how to configure and use the backannotation feature.
