How to generate verilog code for thisbelow function using HDL coder?
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I want to know ,how to generate the verilog code for the below function(divide) using hdl coder.?
T = numerictype('Signed', false,...
'WordLength', 80,...
'FractionLength', 83);
a = fi(20);
b = fi(2);
c = divide(T, a, b);
Thank you.
回答（1 个）
Bharath Venkataraman
2022-5-23
0 个投票
You can use the real divide hdl optimized block. Other options include the reciprocal block followed by a multiply or the divide block in Simulink.
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2022-5-23
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